From patchwork Mon Oct 10 09:53:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen (ThunderTown)" X-Patchwork-Id: 13002413 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0557AC433FE for ; Mon, 10 Oct 2022 09:56:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DU4nmdxzAqbpRjubmjqRd7gtbIS5UWnONqSF+DVoavc=; b=WLBq51b5pXfrdV u0piaYW6z0HpxuFRfng6NsfhLbKXuhMMQzlryaAwrVHk0l/0qHExajJA3Mnpcr3jyvyhjuDvwsPOs eukbCxPKuP2nvFCqrROyNUB9NnEQOZz80tEhoP5IjqCAd/Ij7/nLd9H4y+iS+Vs78tTWBTQhZClw7 j0YHvm+AEHgyq/Hi+cJpwIoXhzhEIjf8ANBtdpQAaKPzoz2iJX9eVFvDuk6OC1t8HTDexXD/kqI2l olXBZbclIQX/huhZdT5sRDusrX76sRCebw8ozvM8tZRaZL9AvJnt++BjzHjX8QAWENVwKxErEi3+B QkEzYjoZ+j60EHoJ/DzA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ohpVF-000HDh-Hl; Mon, 10 Oct 2022 09:55:17 +0000 Received: from szxga01-in.huawei.com ([45.249.212.187]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ohpV6-000H9v-6k for linux-arm-kernel@lists.infradead.org; Mon, 10 Oct 2022 09:55:10 +0000 Received: from dggpemm500020.china.huawei.com (unknown [172.30.72.53]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4MmDg86WgYzmVBd; Mon, 10 Oct 2022 17:50:28 +0800 (CST) Received: from dggpemm500006.china.huawei.com (7.185.36.236) by dggpemm500020.china.huawei.com (7.185.36.49) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Mon, 10 Oct 2022 17:55:01 +0800 Received: from thunder-town.china.huawei.com (10.174.178.55) by dggpemm500006.china.huawei.com (7.185.36.236) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Mon, 10 Oct 2022 17:55:00 +0800 From: Zhen Lei To: Russell King , , CC: Zhen Lei Subject: [PATCH v2 2/2] ARM: Make the dumped instructions are consistent with the disassembled ones Date: Mon, 10 Oct 2022 17:53:46 +0800 Message-ID: <20221010095346.1957-3-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.37.3.windows.1 In-Reply-To: <20221010095346.1957-1-thunder.leizhen@huawei.com> References: <20221010095346.1957-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.178.55] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggpemm500006.china.huawei.com (7.185.36.236) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221010_025508_441553_8B0763F3 X-CRM114-Status: GOOD ( 12.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In ARM, the mapping of instruction memory is always little-endian, except some BE-32 supported ARM architectures. Such as ARMv7-R, its instruction endianness may be BE-32. Of course, its data endianness will also be BE-32 mode. Due to two negatives make a positive, the instruction stored in the register after reading is in little-endian format. But for the case of BE-8, the instruction endianness is LE, the instruction stored in the register after reading is in big-endian format, which is inconsistent with the disassembled one. For example: The content of disassembly: c0429ee8: e3500000 cmp r0, #0 c0429eec: 159f2044 ldrne r2, [pc, #68] c0429ef0: 108f2002 addne r2, pc, r2 c0429ef4: 1882000a stmne r2, {r1, r3} c0429ef8: e7f000f0 udf #0 The output of undefined instruction exception: Internal error: Oops - undefined instruction: 0 [#1] SMP ARM ... ... Code: 000050e3 44209f15 02208f10 0a008218 (f000f0e7) This inconveniences the checking of instructions. What's worse is that, for somebody who don't know about this, might think the instructions are all broken. So, when CONFIG_CPU_ENDIAN_BE8=y, let's convert the instructions to little-endian format before they are printed. The conversion result is as follows: Code: e3500000 159f2044 108f2002 1882000a (e7f000f0) Signed-off-by: Zhen Lei --- arch/arm/kernel/traps.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 34aa80c09c508c1..50b00c9091f079d 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -193,6 +193,13 @@ static void dump_instr(const char *lvl, struct pt_regs *regs) bad = get_user(val, &((u32 __user *)addr)[i]); } + if (IS_ENABLED(CONFIG_CPU_ENDIAN_BE8)) { + if (thumb) + val = (__force unsigned int)cpu_to_le16(val); + else + val = (__force unsigned int)cpu_to_le32(val); + } + if (!bad) p += sprintf(p, i == 0 ? "(%0*x) " : "%0*x ", width, val);