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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: vQmj7R1nU3nKnGQE3PFAskt7t2Vg3Umrx8PE816gd/w7Wv9BBbo7vzuz9YO9L1GIYR52y5vgFsKeAXu7ky4EvAuZdrnDf6SD1qCAOnACAO9JSFqQBzB24nl3Zo/6qNjXXnVuKgNf2KJ2lc3YY+YpF9dJXzp31wDSxzcwqFmyo/xkaZRmBcG+XtM1uxLw30hWRnw9OmziIhf19Ha7naMaHX4iF17hX8PfGmTQq4XDfVYRv19MazmmBfMKdNneb0F0wrRfpyqaZVCcgjVA7aq65wP3reGwYQrZKz5cAdZy0lqF2SxyUf6nmgQ0JzBdy7ZjiIvfsfqFQLzgZGTqKZM322aEhRzgd8W1ZP3L5bTq2gGjoBWY28W3EDsCfEFUrmpAACbGEcP2CAhHpAvmBegkj+wRFwt/rw+L3mODwNwLo61d7piXgi8u5FcUepu2pt+o/rp1HOBpo2BoctL3ZZyW9Aldc5+OxfO/L5vn9wpJ1AJUoqwbGQVFcg/umjrSxOoUlWwaW4FXnHrvh1fXUfaMo9h5Pn7dLkCQ2u1ToEXiV7yViIFeDoPZhU1CLS4oPp8BHw5P3VrCIACrfeTWnDOzfqpHlb+r85XGuVLJEr1f7kdBqBQMmPVTGn14s+xJ9zVgnMNIH5KFVeUoIYJXqyb9ll2vmqxgIWs3z7rFMiuBJmcydQaZM2Dr55ozIV9x8uTSCEOw21LvJRLP/giT2PqxwuR1IosciiZnL0s6TlxWgTFdsOhkPfBgcOFfdGlgMl3ArkHFh++PDbNxEd8/CEvmRBF3kV6F7PTg80Dej3Xmbptsags/i9pGUsoK7SqOq04UdQPgh6IuOAgbfHxBY+Stup2H4ivzeEI9ICHFEHohPY6PP5bxKpnlXT+4m+tE7BoBVLqw2RztN7atCfwSsdkIl9tEcZ+x8L2pVLR+BntUPY/N/TlmafZ1ZlV9iJz94evtbFklevNUHUHRASO4tX5nM4dz8+yqBfCBQoVw6+5k5R1842bmnOzsVGmA+ULAL7z86qcAHSMZPq2QoHZm9Ns37LYeE44H+1OZJZE57J/MvV9w+XFX4NJ5E2p8oP1LK9GPiw7MQjcZLubLHOwMQm48H6GYh/mR7gzdUm15qoo5wQexs4QJ7tJx4Psmy9+9cHX74TJomEU3TwaBnsEXahrfS96H/ZVb5INxeYu/HYJqhCTp8nPL24x/fh+FFMyecs5IZF4FbcfqwJXzduYnlhRtU2UXyk1ZYmZhhNrwqs0mwuSlpDiMmMgYiJ6SRyKPrHSQtlU4UaUBiH5zMT6UnfJSyLwy4YEpPPQU2nwo2lBcarWLYNfUW5vzM8S81J9weiBdiNZ2MpCaANeP4jonpCODEFHAyNxEbgvz1ZUqfDtJkcEr0OPACfLizweNgRcxlQwuyXrX5+xBZ5NDGeripzw8e/hKDnPFP62cveUs3Wj8sxnwb4OUprOasc/8RUbOqKnxTx+fCsvgvNIQ0xWh4BZb2zlrGEkSGzwRKRX8zYh+f3U8uTrT8qFQb38zkY+8Br/zZcE3H5IkLAzoC6/z/hVU/+j1iImzAO45pYudMYrXCp1rMVsWdlBfQ4CO67I7SDpt X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 49754669-1f02-4a7d-3ab1-08dab012b984 X-MS-Exchange-CrossTenant-AuthSource: AM7PR04MB7046.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Oct 2022 07:39:29.7977 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: q7zTplxcey6Y0SJbvDiUvvU4efq7PDfg9PFjZ8HDsLJO4uGjuraFxJ79p7TxFrU7IA0aRIW2+swg6/h7CW6Flg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB8296 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221017_003932_823072_B568D61F X-CRM114-Status: GOOD ( 21.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Freescale i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. It is used to access peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems, like I2C controller, PWM controller, MIPI DSI controller and Control and Status Registers (CSR) module. Reference simple-pm-bus bindings and add Freescale i.MX8qxp pixel link MSI bus specific bindings. Reviewed-by: Rob Herring Signed-off-by: Liu Ying --- v3->v4: * Add child nodes in the example MSI bus node of the MSI bus dt-binding. (Krzysztof) * Resend v4 to imply this patch is based on v6.0-rc1 so that there are not any dependencies. (Rob) * Resend v4 based on v6.1-rc1. (Greg) * Add Rob's R-b tag. v2->v3: * Add a pattern property to allow child nodes. (Rob) v1->v2: Address Krzysztof's comments: * Add a select to explicitly select the MSI bus dt-binding. * List 'simple-pm-bus' explicitly as one item of compatible strings. * Require compatible and reg properties. * Put reg property just after compatible property in example. .../bus/fsl,imx8qxp-pixel-link-msi-bus.yaml | 232 ++++++++++++++++++ 1 file changed, 232 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml diff --git a/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml b/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml new file mode 100644 index 000000000000..b568d0ce438d --- /dev/null +++ b/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml @@ -0,0 +1,232 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus + +maintainers: + - Liu Ying + +description: | + i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os + sitting together with the PHYs. It is not the same as the MSI bus coming + from i.MX8 System Controller Unit (SCU) which is used to control power, + clock and reset through the i.MX8 Distributed Slave System Controller (DSC). + + i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks, + that is, MSI clock and AHB clock, need to be enabled so that peripherals + connected to the bus can be accessed. Also, the bus is part of a power + domain. The power domain needs to be enabled before the peripherals can + be accessed. + + Peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems, + like I2C controller, PWM controller, MIPI DSI controller and Control and + Status Registers (CSR) module, are accessed through the bus. + + The i.MX System Controller Firmware (SCFW) owns and uses the i.MX8qm/qxp + pixel link MSI bus controller and does not allow SCFW user to control it. + So, the controller's registers cannot be accessed by SCFW user. Hence, + the interrupts generated by the controller don't make any sense from SCFW + user's point of view. + +allOf: + - $ref: simple-pm-bus.yaml# + +# We need a select here so we don't match all nodes with 'simple-pm-bus'. +select: + properties: + compatible: + contains: + enum: + - fsl,imx8qxp-display-pixel-link-msi-bus + - fsl,imx8qm-display-pixel-link-msi-bus + required: + - compatible + +properties: + compatible: + items: + - enum: + - fsl,imx8qxp-display-pixel-link-msi-bus + - fsl,imx8qm-display-pixel-link-msi-bus + - const: simple-pm-bus + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: master gated clock from system + - description: AHB clock + + clock-names: + items: + - const: msi + - const: ahb + +patternProperties: + "^.*@[0-9a-f]+$": + description: Devices attached to the bus + type: object + properties: + reg: + maxItems: 1 + + required: + - reg + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include + #include + bus@56200000 { + compatible = "fsl,imx8qxp-display-pixel-link-msi-bus", "simple-pm-bus"; + reg = <0x56200000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&dc0_irqsteer>; + interrupts = <320>; + ranges; + clocks = <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>, + <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>; + clock-names = "msi", "ahb"; + power-domains = <&pd IMX_SC_R_DC_0>; + + syscon@56221000 { + compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd"; + reg = <0x56221000 0x1000>; + clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>; + clock-names = "ipg"; + + pxl2dpi { + compatible = "fsl,imx8qxp-pxl2dpi"; + fsl,sc-resource = ; + power-domains = <&pd IMX_SC_R_MIPI_0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>; + }; + + mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 { + reg = <1>; + remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>; + }; + + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>; + }; + }; + }; + }; + + ldb { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + + channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&mipi_lvds_0_phy>; + phy-names = "lvds_phy"; + + port@0 { + reg = <0>; + + mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>; + }; + }; + + port@1 { + reg = <1>; + + /* ... */ + }; + }; + + channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&mipi_lvds_0_phy>; + phy-names = "lvds_phy"; + + port@0 { + reg = <0>; + + mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>; + }; + }; + + port@1 { + reg = <1>; + + /* ... */ + }; + }; + }; + }; + + clock-controller@56223004 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223004 0x4>; + #clock-cells = <1>; + clocks = <&mipi_lvds_0_ipg_clk>; + clock-indices = ; + clock-output-names = "mipi_lvds_0_di_mipi_lvds_regs_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + phy@56228300 { + compatible = "fsl,imx8qxp-mipi-dphy"; + reg = <0x56228300 0x100>; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>; + clock-names = "phy_ref"; + #phy-cells = <0>; + fsl,syscon = <&mipi_lvds_0_csr>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + };