From patchwork Thu Oct 20 23:01:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 13014118 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A10C6C433FE for ; Thu, 20 Oct 2022 23:02:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=fb72Q7tRhc0B0wEgIHho8PD5pHSYHN7JoMQUm+yauUo=; b=Xbp59LPj6hTizt nry3Nmb2+GqDrJLKWQieIWoZKSpA3qBygd+pVLBpQ85IiF34AvtXGOKfqeZR0Mi0HgqpeWrN3+91E SObSvS5OncJ8Z5orlRR468EZPo7M0tJ9gtc0Z24uXv3Kw7F3uzdsNj5G25Lw4rtMuhfOOGh8jyj4B rA7WKSaw9/j+sybf20DGdHfzXcCV8JFfhQf99pzzpR4rpB6ScoB2K3pL2E2WLlbzGTqUUnBhA8bs7 FGq/lN97MLd2a+Rt73XVpl4GHu7Vw6NoRIboua3xdbNZrqFe4nkECgSfx4ISAQrrDfPhQWYO4hVIR LxzUZVXtxzg2dMX32XCA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oleXR-002Sfl-Tq; Thu, 20 Oct 2022 23:01:22 +0000 Received: from mail-qt1-x82a.google.com ([2607:f8b0:4864:20::82a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oleXO-002Scb-GX for linux-arm-kernel@lists.infradead.org; Thu, 20 Oct 2022 23:01:20 +0000 Received: by mail-qt1-x82a.google.com with SMTP id r19so620950qtx.6 for ; Thu, 20 Oct 2022 16:01:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=WY859iR4eUBbX0oEC3iSq/WIpqFnIAgknLhojitZ9do=; b=UUVH0MEuV0cUhceZ1YZaqhZBc4aJO1HZEev18yl5ybsghOkxvQdbUENJP3zbuUwedK xKkRw74ZSn+Ei9vqfjWT12gP6gU635+OL43HbRbxYLnZOTnuflVfv28tn/mFRk2UYbq3 aWrsip8YmhHIGKPKsYFwGDTr48YnNko4UNIxIEPII9TM6NirzN3U6k5mNkQX9bMcb3AE WDkt2uI5APiaVWhhra5n2wOCdPxRzkJY2Es+24QUJStBW34vY+kTCVBgyFj4c8n4xN+j S6EiV4OCnRWImRThYK4Iex7h22s3lwCDtLRG5XP4SLUMYFyLi/JjPQcP7KZZStJViyOi icyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=WY859iR4eUBbX0oEC3iSq/WIpqFnIAgknLhojitZ9do=; b=CED03dotVWmUc33pqdYV+abQ7DE3XymqLNI9Yi/08N06xr8grC90d3zZLmzpXKHccg rVzO8udZXZhT0gsKk0216EAWY9QSv6hReaqfktG/LneRULMLSDSkCgAq4xcLicHf9fCf Ds2L1zFNtNBaYiI7sM8jEhHFtUbOj1NvZiRQQ2i9b/BL1x1ukHISLarYm4QUYvnKQMl0 y2Kna5OsAZuNtwdpnEWZgblSJRYZBL6n0iHkHGxa2wWsTNWeO9dNzrtZiEQaedKhCFAZ m1RElfuddn/XAuGelfvcJt3xc0Aw7Y8T+l1qrnvqhMW7KDBkvkOiMFAmsNIIiw0H0D3Q iZ0g== X-Gm-Message-State: ACrzQf0sHFWkQiHPaNON42oxdAJzyiEI4GwQIDnt36lZBBqO/D+FnZmh WEysO8evER25jDgj120KHSA= X-Google-Smtp-Source: AMsMyM5qVroUht2IpvHg+0GBnECLjoWuJmrjjukIFmTtYLyYbGXTU8Gs7WVy2QQzYP7quhEnIIrEBg== X-Received: by 2002:ac8:5f07:0:b0:39c:f911:7a8c with SMTP id x7-20020ac85f07000000b0039cf9117a8cmr12236136qta.218.1666306876062; Thu, 20 Oct 2022 16:01:16 -0700 (PDT) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id de20-20020a05620a371400b006ef1a8f1b81sm669343qkb.5.2022.10.20.16.01.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 16:01:15 -0700 (PDT) From: Florian Fainelli To: stable@vger.kernel.org Cc: James Morse , Ard Biesheuvel , Will Deacon , Florian Fainelli , Catalin Marinas , Jonathan Corbet , Greg Kroah-Hartman , Zenghui Yu , Ionela Voinescu , Shreyas K K , Marc Zyngier , Joey Gouly , Reiji Watanabe , Alexandru Elisei , linux-arm-kernel@lists.infradead.org (moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-kernel@vger.kernel.org (open list), Sasha Levin Subject: [PATCH stable 4.9] arm64: errata: Remove AES hwcap for COMPAT tasks Date: Thu, 20 Oct 2022 16:01:05 -0700 Message-Id: <20221020230110.1255660-1-f.fainelli@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221020_160118_588662_6C5485FE X-CRM114-Status: GOOD ( 23.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: James Morse commit 44b3834b2eed595af07021b1c64e6f9bc396398b upstream Cortex-A57 and Cortex-A72 have an erratum where an interrupt that occurs between a pair of AES instructions in aarch32 mode may corrupt the ELR. The task will subsequently produce the wrong AES result. The AES instructions are part of the cryptographic extensions, which are optional. User-space software will detect the support for these instructions from the hwcaps. If the platform doesn't support these instructions a software implementation should be used. Remove the hwcap bits on affected parts to indicate user-space should not use the AES instructions. Acked-by: Ard Biesheuvel Signed-off-by: James Morse Link: https://lore.kernel.org/r/20220714161523.279570-3-james.morse@arm.com Signed-off-by: Will Deacon [florian: resolved conflicts in arch/arm64/tools/cpucaps and cpu_errata.c] Signed-off-by: Florian Fainelli Change-Id: I651a0db2e9d2f304d210ae979ae586e7dcc9744d Signed-off-by: Florian Fainelli --- Documentation/arm64/silicon-errata.txt | 2 ++ arch/arm64/Kconfig | 16 ++++++++++++++++ arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/kernel/cpu_errata.c | 16 ++++++++++++++++ arch/arm64/kernel/cpufeature.c | 13 ++++++++++++- 5 files changed, 48 insertions(+), 2 deletions(-) diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index 47df2c25302a..e6aced550e23 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -53,7 +53,9 @@ stable kernels. | ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 | | ARM | Cortex-A57 | #852523 | N/A | | ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 | +| ARM | Cortex-A57 | #1742098 | ARM64_ERRATUM_1742098 | | ARM | Cortex-A72 | #853709 | N/A | +| ARM | Cortex-A72 | #1655431 | ARM64_ERRATUM_1742098 | | ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 | | ARM | Cortex-A76 | #1188873 | ARM64_ERRATUM_1188873 | | ARM | MMU-500 | #841119,#826419 | N/A | diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 6d12c3b78777..3e0be8648ce7 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -455,6 +455,22 @@ config ARM64_ERRATUM_1188873 If unsure, say Y. +config ARM64_ERRATUM_1742098 + bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" + depends on COMPAT + default y + help + This option removes the AES hwcap for aarch32 user-space to + workaround erratum 1742098 on Cortex-A57 and Cortex-A72. + + Affected parts may corrupt the AES state if an interrupt is + taken between a pair of AES instructions. These instructions + are only present if the cryptography extensions are present. + All software should have a fallback implementation for CPUs + that don't implement the cryptography extensions. + + If unsure, say Y. + config CAVIUM_ERRATUM_22375 bool "Cavium erratum 22375, 24313" default y diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index 9935e55a3cc7..91d365d87694 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -40,7 +40,8 @@ #define ARM64_MISMATCHED_CACHE_TYPE 19 #define ARM64_WORKAROUND_1188873 20 #define ARM64_SPECTRE_BHB 21 +#define ARM64_WORKAROUND_1742098 22 -#define ARM64_NCAPS 22 +#define ARM64_NCAPS 23 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index f0cdf21b1006..17208f1b10a9 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -448,6 +448,14 @@ static const struct midr_range arm64_bp_harden_smccc_cpus[] = { #endif +#ifdef CONFIG_ARM64_ERRATUM_1742098 +static struct midr_range broken_aarch32_aes[] = { + MIDR_RANGE(MIDR_CORTEX_A57, 0, 1, 0xf, 0xf), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), + {}, +}; +#endif + const struct arm64_cpu_capabilities arm64_errata[] = { #if defined(CONFIG_ARM64_ERRATUM_826319) || \ defined(CONFIG_ARM64_ERRATUM_827319) || \ @@ -567,6 +575,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .cpu_enable = spectre_bhb_enable_mitigation, #endif }, +#ifdef CONFIG_ARM64_ERRATUM_1742098 + { + .desc = "ARM erratum 1742098", + .capability = ARM64_WORKAROUND_1742098, + CAP_MIDR_RANGE_LIST(broken_aarch32_aes), + .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, + }, +#endif { } }; diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 9b7e7d2f236e..0f62adbe1b07 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -885,6 +886,14 @@ static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); } +static void elf_hwcap_fixup(void) +{ +#ifdef CONFIG_ARM64_ERRATUM_1742098 + if (cpus_have_const_cap(ARM64_WORKAROUND_1742098)) + compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; +#endif /* ARM64_ERRATUM_1742098 */ +} + static const struct arm64_cpu_capabilities arm64_features[] = { { .desc = "GIC system register CPU interface", @@ -1304,8 +1313,10 @@ void __init setup_cpu_features(void) mark_const_caps_ready(); setup_elf_hwcaps(arm64_elf_hwcaps); - if (system_supports_32bit_el0()) + if (system_supports_32bit_el0()) { setup_elf_hwcaps(compat_elf_hwcaps); + elf_hwcap_fixup(); + } /* Advertise that we have computed the system capabilities */ set_sys_caps_initialised();