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[5/8] arm64: Add compat hwcap ASIMDBF16

Message ID 20221026055813.13484-6-amit.kachhap@arm.com (mailing list archive)
State New, archived
Headers show
Series arm64: Expose compat Armv8 AArch32 features | expand

Commit Message

Amit Daniel Kachhap Oct. 26, 2022, 5:58 a.m. UTC 
This hwcap is earlier added for 32-bit native arm kernel and hence the
corresponding changes added in 32-bit compat arm64 kernel.
Brain 16-bit floating-point storage format is a feature (FEAT_AA32BF16)
present in AArch32 state for Armv8 and is represented by ISAR6.BF16
identification register. Similar feature (FEAT_BF16) exist for AArch64
state and is already advertised in arm64 kernel.

Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
---
 arch/arm64/include/asm/hwcap.h | 1 +
 arch/arm64/kernel/cpufeature.c | 3 ++-
 arch/arm64/kernel/cpuinfo.c    | 1 +
 3 files changed, 4 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
index 8d944397a9a3..62e7eadecb30 100644
--- a/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@ -35,6 +35,7 @@ 
 #define COMPAT_HWCAP_ASIMDHP	(1 << 23)
 #define COMPAT_HWCAP_ASIMDDP	(1 << 24)
 #define COMPAT_HWCAP_ASIMDFHM	(1 << 25)
+#define COMPAT_HWCAP_ASIMDBF16	(1 << 26)
 
 #define COMPAT_HWCAP2_AES	(1 << 0)
 #define COMPAT_HWCAP2_PMULL	(1 << 1)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 8b6d0ed571ce..213f41cb477b 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -528,7 +528,7 @@  static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
 
 static const struct arm64_ftr_bits ftr_id_isar6[] = {
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
-	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
@@ -2851,6 +2851,7 @@  static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
 	HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
 	HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_DP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP),
 	HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_FHM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM),
+	HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16),
 #endif
 	{},
 };
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 23afcd80c7fd..a76e66947bcb 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -147,6 +147,7 @@  static const char *const compat_hwcap_str[] = {
 	[COMPAT_KERNEL_HWCAP(ASIMDHP)]	= "asimdhp",
 	[COMPAT_KERNEL_HWCAP(ASIMDDP)]	= "asimddp",
 	[COMPAT_KERNEL_HWCAP(ASIMDFHM)]	= "asimdfhm",
+	[COMPAT_KERNEL_HWCAP(ASIMDBF16)]	= "asimdbf16",
 };
 
 #define COMPAT_KERNEL_HWCAP2(x)	const_ilog2(COMPAT_HWCAP2_ ## x)