| Message ID | 20221026090957.180592-2-s-vadapalli@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for QSGMII mode for J721e CPSW9G to am65-cpsw driver | expand |
On Wed, Oct 26, 2022 at 02:39:55PM +0530, Siddharth Vadapalli wrote: > Update bindings for TI K3 J721e SoC which contains 9 ports (8 external > ports) CPSW9G module and add compatible for it. Don't repeat 'bindings' in the subject, space is precious: dt-bindings: net: ti: k3-am654-cpsw-nuss: Add J721e CPSW9G support Otherwise, Reviewed-by: Rob Herring <robh@kernel.org> > > Changes made: > - Add new compatible ti,j721e-cpswxg-nuss for CPSW9G. > - Extend pattern properties for new compatible. > - Change maximum number of CPSW ports to 8 for new compatible. > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> > --- > .../bindings/net/ti,k3-am654-cpsw-nuss.yaml | 33 ++++++++++++++++--- > 1 file changed, 29 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml index 821974815dec..900063411a20 100644 --- a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml +++ b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml @@ -57,6 +57,7 @@ properties: - ti,am654-cpsw-nuss - ti,j7200-cpswxg-nuss - ti,j721e-cpsw-nuss + - ti,j721e-cpswxg-nuss - ti,am642-cpsw-nuss reg: @@ -111,7 +112,7 @@ properties: const: 0 patternProperties: - "^port@[1-4]$": + "^port@[1-8]$": type: object description: CPSWxG NUSS external ports @@ -121,7 +122,7 @@ properties: properties: reg: minimum: 1 - maximum: 4 + maximum: 8 description: CPSW port number phys: @@ -186,12 +187,36 @@ allOf: properties: compatible: contains: - const: ti,j7200-cpswxg-nuss + const: ti,j721e-cpswxg-nuss then: properties: ethernet-ports: patternProperties: - "^port@[3-4]$": false + "^port@[5-8]$": false + "^port@[1-4]$": + properties: + reg: + minimum: 1 + maximum: 4 + + - if: + not: + properties: + compatible: + contains: + enum: + - ti,j721e-cpswxg-nuss + - ti,j7200-cpswxg-nuss + then: + properties: + ethernet-ports: + patternProperties: + "^port@[3-8]$": false + "^port@[1-2]$": + properties: + reg: + minimum: 1 + maximum: 2 additionalProperties: false
Update bindings for TI K3 J721e SoC which contains 9 ports (8 external ports) CPSW9G module and add compatible for it. Changes made: - Add new compatible ti,j721e-cpswxg-nuss for CPSW9G. - Extend pattern properties for new compatible. - Change maximum number of CPSW ports to 8 for new compatible. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> --- .../bindings/net/ti,k3-am654-cpsw-nuss.yaml | 33 ++++++++++++++++--- 1 file changed, 29 insertions(+), 4 deletions(-)