From patchwork Fri Oct 28 13:14:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Machon X-Patchwork-Id: 13023592 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 713B3ECAAA1 for ; Fri, 28 Oct 2022 13:06:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=r83n0LNW0XaITfbqWpeDePN8pxiZEkfEZrQsiCTk0Vk=; b=R+1ZeuKcL/+RQR 8qXGOFZB5O8zNTH2sU7hi7YqgQI5mI4wHYpCvE9rAQUpDZG8IjcD8baZaLiVQGyiY4tYOOIzK4SNQ r36jvlRZ4Z6n/DodfWAEgvZJ4m0y73EqpP/mKCsiBsLkPTJnj2e56zrSZiCISFZa8VDVBMao1W8uA nocx6/aLfOir9xwCGh8jKr9W8Enictsm7qlZAjd80VvaxC3+X80Flj0jMkMpIHMvr54GL5ie8dSyC NCh1xIWT4nX3JNpk6EddI+G9lS7qbo5u+AXI9akasNr/c4EAuoM5qPTITEH3uHyh3ehuSv2j3uVME XdOjXDxnjkjmnDNUmA3A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ooP32-00HDW2-4S; Fri, 28 Oct 2022 13:05:20 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ooP2h-00HDN3-PG for linux-arm-kernel@lists.infradead.org; Fri, 28 Oct 2022 13:05:01 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1666962299; x=1698498299; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rVdNzdBQO+N6n0DeTiUUzVhpCEMcLGmACZM8CQ8W5rc=; b=DPb++NjAkNqSkCE6kLm8ooR3+YydYGle4Z9Y/mgUgNDKsisjDhqCEXj1 AAtHx7hBKMzA+uvuOnSEdZKHpz+x9QJUj1wggsf5PFrPhmW9Zhg/uQV8l 8vXfGcXjsUK4lcS/aHuyyrTTqYWKgNH5pmrkoL3XObGTlc4xfAnSbr/d9 xVbPQ/urazwXRSOPVgI610azYKFt/3z9Hvoiwe+nLuTuqea9pCmvy4sRq D9zsIElmbBF5tW+cC2ZOuP4K9fVdds31lMw5EEJt3ARQIk4ZplwZv/nLA T0VuxNcn/9jshiJQUGUlSw2diUjTxuE39yOwQK3U5bImFDz7Tuq5KBcN4 A==; X-IronPort-AV: E=Sophos;i="5.95,221,1661842800"; d="scan'208";a="120801638" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Oct 2022 06:04:54 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 28 Oct 2022 06:04:54 -0700 Received: from DEN-LT-70577.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 28 Oct 2022 06:04:50 -0700 From: Daniel Machon To: CC: , , , , , , , , , , , , , , , , , Subject: [PATCH net-next v5 6/6] net: microchip: sparx5: add support for offloading default prio Date: Fri, 28 Oct 2022 15:14:03 +0200 Message-ID: <20221028131403.1055694-7-daniel.machon@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221028131403.1055694-1-daniel.machon@microchip.com> References: <20221028131403.1055694-1-daniel.machon@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221028_060459_961279_744F5697 X-CRM114-Status: GOOD ( 14.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for offloading default prio {ETHERTYPE, 0, prio}. Signed-off-by: Daniel Machon --- .../ethernet/microchip/sparx5/sparx5_dcb.c | 12 ++++++++++ .../ethernet/microchip/sparx5/sparx5_port.c | 23 +++++++++++++++++++ .../ethernet/microchip/sparx5/sparx5_port.h | 5 ++++ 3 files changed, 40 insertions(+) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_dcb.c b/drivers/net/ethernet/microchip/sparx5/sparx5_dcb.c index 283d5f338e0e..df2374e64b72 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_dcb.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_dcb.c @@ -34,6 +34,13 @@ static int sparx5_dcb_app_validate(struct net_device *dev, int err = 0; switch (app->selector) { + /* Default priority checks */ + case IEEE_8021QAZ_APP_SEL_ETHERTYPE: + if (app->protocol != 0) + err = -EINVAL; + else if (app->priority >= SPX5_PRIOS) + err = -ERANGE; + break; /* Dscp checks */ case IEEE_8021QAZ_APP_SEL_DSCP: if (app->protocol > 63) @@ -122,6 +129,11 @@ static int sparx5_dcb_app_update(struct net_device *dev) dscp_map = &qos.dscp.map; pcp_map = &qos.pcp.map; + /* Get default prio. */ + qos.default_prio = dcb_ieee_getapp_default_prio_mask(dev); + if (qos.default_prio) + qos.default_prio = fls(qos.default_prio) - 1; + /* Get dscp ingress mapping */ for (i = 0; i < ARRAY_SIZE(dscp_map->map); i++) { app_itr.selector = IEEE_8021QAZ_APP_SEL_DSCP; diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c index fb5e321c4896..73ebe76d7e50 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c @@ -1151,6 +1151,7 @@ int sparx5_port_qos_set(struct sparx5_port *port, { sparx5_port_qos_dscp_set(port, &qos->dscp); sparx5_port_qos_pcp_set(port, &qos->pcp); + sparx5_port_qos_default_set(port, qos); return 0; } @@ -1220,3 +1221,25 @@ int sparx5_port_qos_dscp_set(const struct sparx5_port *port, return 0; } + +int sparx5_port_qos_default_set(const struct sparx5_port *port, + const struct sparx5_port_qos *qos) +{ + struct sparx5 *sparx5 = port->sparx5; + + /* Set default prio and dp level */ + spx5_rmw(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_SET(qos->default_prio) | + ANA_CL_QOS_CFG_DEFAULT_DP_VAL_SET(0), + ANA_CL_QOS_CFG_DEFAULT_QOS_VAL | + ANA_CL_QOS_CFG_DEFAULT_DP_VAL, + sparx5, ANA_CL_QOS_CFG(port->portno)); + + /* Set default pcp and dei for untagged frames */ + spx5_rmw(ANA_CL_VLAN_CTRL_PORT_PCP_SET(0) | + ANA_CL_VLAN_CTRL_PORT_DEI_SET(0), + ANA_CL_VLAN_CTRL_PORT_PCP | + ANA_CL_VLAN_CTRL_PORT_DEI, + sparx5, ANA_CL_VLAN_CTRL(port->portno)); + + return 0; +} diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_port.h b/drivers/net/ethernet/microchip/sparx5/sparx5_port.h index a0cd53fa3ad0..588eecff59f8 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.h @@ -114,6 +114,7 @@ struct sparx5_port_qos_dscp { struct sparx5_port_qos { struct sparx5_port_qos_pcp pcp; struct sparx5_port_qos_dscp dscp; + u8 default_prio; }; int sparx5_port_qos_set(struct sparx5_port *port, struct sparx5_port_qos *qos); @@ -123,4 +124,8 @@ int sparx5_port_qos_pcp_set(const struct sparx5_port *port, int sparx5_port_qos_dscp_set(const struct sparx5_port *port, struct sparx5_port_qos_dscp *qos); + +int sparx5_port_qos_default_set(const struct sparx5_port *port, + const struct sparx5_port_qos *qos); + #endif /* __SPARX5_PORT_H__ */