| Message ID | 20221031092020.532456-1-pierre.gondois@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Update cache properties for arm64 DTS | expand |
On 31/10/22 22:20, Pierre Gondois wrote: > The DeviceTree Specification v0.3 specifies that the cache node > 'compatible' and 'cache-level' properties are 'required'. Cf. > s3.8 Multi-level and Shared Cache Nodes > > The recently added init_of_cache_level() function checks > these properties. Add them if missing. > > Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> For ac5-98dx25xx.dtsi Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > --- > arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 1 + > arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 1 + > arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 2 ++ > arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 2 ++ > 4 files changed, 6 insertions(+) > > diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi > index 80b44c7df56a..d4770acec6ac 100644 > --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi > +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi > @@ -49,6 +49,7 @@ cpu1: cpu@1 { > > l2: l2-cache { > compatible = "cache"; > + cache-level = <2>; > }; > }; > > diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi > index fcab5173fe67..990f70303fe6 100644 > --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi > @@ -51,6 +51,7 @@ l2: l2-cache { > cache-size = <0x80000>; > cache-line-size = <64>; > cache-sets = <512>; > + cache-level = <2>; > }; > }; > > diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi > index 3db427122f9e..a7b8e001cc9c 100644 > --- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi > @@ -81,6 +81,7 @@ l2_0: l2-cache0 { > cache-size = <0x80000>; > cache-line-size = <64>; > cache-sets = <512>; > + cache-level = <2>; > }; > > l2_1: l2-cache1 { > @@ -88,6 +89,7 @@ l2_1: l2-cache1 { > cache-size = <0x80000>; > cache-line-size = <64>; > cache-sets = <512>; > + cache-level = <2>; > }; > }; > }; > diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi > index 68782f161f12..7740098fd108 100644 > --- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi > @@ -81,6 +81,7 @@ l2_0: l2-cache0 { > cache-size = <0x80000>; > cache-line-size = <64>; > cache-sets = <512>; > + cache-level = <2>; > }; > > l2_1: l2-cache1 { > @@ -88,6 +89,7 @@ l2_1: l2-cache1 { > cache-size = <0x80000>; > cache-line-size = <64>; > cache-sets = <512>; > + cache-level = <2>; > }; > }; > };
On 31/10/2022 05:20, Pierre Gondois wrote: > The DeviceTree Specification v0.3 specifies that the cache node > 'compatible' and 'cache-level' properties are 'required'. Cf. > s3.8 Multi-level and Shared Cache Nodes > > The recently added init_of_cache_level() function checks > these properties. Add them if missing. > > Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Your threading is broken. Best regards, Krzysztof
Pierre Gondois <pierre.gondois@arm.com> writes: > The DeviceTree Specification v0.3 specifies that the cache node > 'compatible' and 'cache-level' properties are 'required'. Cf. > s3.8 Multi-level and Shared Cache Nodes > > The recently added init_of_cache_level() function checks > these properties. Add them if missing. > > Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Applied on mvebu/dt64 Thanks, Gregory > --- > arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 1 + > arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 1 + > arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 2 ++ > arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 2 ++ > 4 files changed, 6 insertions(+) > > diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi > index 80b44c7df56a..d4770acec6ac 100644 > --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi > +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi > @@ -49,6 +49,7 @@ cpu1: cpu@1 { > > l2: l2-cache { > compatible = "cache"; > + cache-level = <2>; > }; > }; > > diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi > index fcab5173fe67..990f70303fe6 100644 > --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi > @@ -51,6 +51,7 @@ l2: l2-cache { > cache-size = <0x80000>; > cache-line-size = <64>; > cache-sets = <512>; > + cache-level = <2>; > }; > }; > > diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi > index 3db427122f9e..a7b8e001cc9c 100644 > --- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi > @@ -81,6 +81,7 @@ l2_0: l2-cache0 { > cache-size = <0x80000>; > cache-line-size = <64>; > cache-sets = <512>; > + cache-level = <2>; > }; > > l2_1: l2-cache1 { > @@ -88,6 +89,7 @@ l2_1: l2-cache1 { > cache-size = <0x80000>; > cache-line-size = <64>; > cache-sets = <512>; > + cache-level = <2>; > }; > }; > }; > diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi > index 68782f161f12..7740098fd108 100644 > --- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi > @@ -81,6 +81,7 @@ l2_0: l2-cache0 { > cache-size = <0x80000>; > cache-line-size = <64>; > cache-sets = <512>; > + cache-level = <2>; > }; > > l2_1: l2-cache1 { > @@ -88,6 +89,7 @@ l2_1: l2-cache1 { > cache-size = <0x80000>; > cache-line-size = <64>; > cache-sets = <512>; > + cache-level = <2>; > }; > }; > }; > -- > 2.25.1 >
diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi index 80b44c7df56a..d4770acec6ac 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -49,6 +49,7 @@ cpu1: cpu@1 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi index fcab5173fe67..990f70303fe6 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi @@ -51,6 +51,7 @@ l2: l2-cache { cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi index 3db427122f9e..a7b8e001cc9c 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi @@ -81,6 +81,7 @@ l2_0: l2-cache0 { cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; }; l2_1: l2-cache1 { @@ -88,6 +89,7 @@ l2_1: l2-cache1 { cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; }; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi index 68782f161f12..7740098fd108 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi @@ -81,6 +81,7 @@ l2_0: l2-cache0 { cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; }; l2_1: l2-cache1 { @@ -88,6 +89,7 @@ l2_1: l2-cache1 { cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; }; }; };
The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> --- arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 1 + arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 1 + arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 2 ++ arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 2 ++ 4 files changed, 6 insertions(+)