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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jan Petrous , =?utf-8?q?Andreas_F=C3=A4rber?= , Matthias Brugger Subject: [PATCH 3/5] net: stmmac: Add CSR clock 500Mhz/800Mhz support Date: Mon, 31 Oct 2022 18:10:50 +0800 Message-Id: <20221031101052.14956-4-clin@suse.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221031101052.14956-1-clin@suse.com> References: <20221031101052.14956-1-clin@suse.com> X-ClientProxiedBy: TYAPR01CA0205.jpnprd01.prod.outlook.com (2603:1096:404:29::25) To VI1PR0402MB3439.eurprd04.prod.outlook.com (2603:10a6:803:4::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR0402MB3439:EE_|VE1PR04MB7261:EE_ X-MS-Office365-Filtering-Correlation-Id: 931a5415-bd00-4a43-e811-08dabb284c66 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: JsKlPQ+7NgaZHfo+WcS2Hfc7GFEi75LJOIwfj89Ku3451ph0Ti9vJnwqCI0eEpbfF7uhOeZ4Y8Tk/cvX3Rvgq9KdxmZqgvCP6Y3OUUrhujgIc3XmwFRCwaWOLkO1mXVCfFrZYcS8OQYoBcoS77/4c6yFbTRjU8Unox3K45HeYyVmGaQfvJ4LJj92Y+PhBhqQrrXv3dAIPxpieZI18dWXMSoBCIfEUUXVh5LZkm7zmibzZwXLBEGTRyMcqXihs7GRCYBJQ1ZwmxY2SYkHu/KhXeMl74BDAhuHqQeqX1Eouk51fervNajicxgx0bsqJ4M2unrzUldbbm8MPPahYM9go66z5ATQBwUMEw3h2NFvJd3/wkwbUuns55Ulpe43+5EM8jq1Lj/ANFCv76hPzXhoqkDhisUGF8SAZRxOqzLqODYQ04dMDwzvlQeQMqZNaV/E5ImbljzjZMGU3fEv0jYBLd89rQHuplJmIpjpknCh9UE397fGA9GP13T1KcPl6m+7y4+OL4MrNObEwNUjsOFPZPCfhHZlpGiYYz2FAKQKZcggfq2MDyv9DjsL+1A93wAWTny9VhJScTvVFZko5r6n63DD2/W/9QSiLZyxtyAHmSK8QEN/hzDv4pdG8sgVips+Q6YazlBgrxWoQ68X2ttdeeGKExGwMib5EzcrkELoHBG1Phm8GB9UrgUsd0RyEi1tTsHizWImVMgFbBRZ9AC6Ng== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VI1PR0402MB3439.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(136003)(396003)(39850400004)(376002)(366004)(346002)(451199015)(6486002)(107886003)(478600001)(110136005)(54906003)(316002)(6666004)(86362001)(8676002)(6506007)(4326008)(66476007)(66946007)(66556008)(2906002)(26005)(38100700002)(41300700001)(6512007)(2616005)(186003)(1076003)(83380400001)(8936002)(36756003)(7416002)(5660300002);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: SxAQujihSr3y4d0bRb4dpAzpxXkHywLWzEoSu+UVtDV388Xr7fp+Yycw7NhgSlVBW/z3e8HGF6N0ca7GxzQyflloUJigSB3q7EjariWS/743/oPdVxYO1GKa50D19chyFIQEnfBs3WzUVX6avHB9WfTeTVC48AZCzL0o7CZFQOrtfgb8Jg5kVdBIixk81KSrhNq3IH69adogphlwMczeBpyEMyNd5D6qC2zgWBlNYTmIaXW1MXMnj5zY+dvSbGmLmAUtL2S12jZIctmLvnBUjxLYvfeNbGPVl3bUjP2t3Nh93AFPL+yWNjwCdP0Wgr3lLJMxfRf+JeD8FI98/Ikk0lmySweoETDswVsQBLxoJqrI2SLP9VPv7SFP6jOZVECxNn5dJxJjYiadVJm9KNlqFukGMEVtlOKA5yozmePQpup7HFcqWC8eYUI2v0JRwQhj5QpDuepOSBtp5ZRM/xpCLDF8Ztb7ky3f59QZdbSVs75bkvAW8KWeJPmpTPbsdWlPIm+/iSXoFytnzSEDXQKlPk5I65aVHjpzSRBGvmkxrQl/FoX+A1EJQjRGjjwvpXZwDgF7mGwAksigTlXAgw23qx+q00jKQWTlLX3i6XOi73rorXZ5KVbp0ulOZwt7dux1TsgNsJVPd9V+w/PpVy+YWkp47AWf+lrpLMayLm8fQFbm7tJY0wceRgbRvKpY8zJ1dijkSpakQ3qnd+I4p36jKg1i8qXCFW5xIA2MEVUvmqE/1f/z66YmKpzmYGQpjp1C5GSx31DJGuX2FNnwrVyfwIfdG2LlDsOEOxS/ynLfTSwuUr9jO8aV/cEuZmCvU4cBU1WKw5lcQi0iPlrNrbRiT1jnHCJtcOslrJoTlStfjPke9HKj77eSqpHBT4fU8GiYDthNxRVsRebBWVypn3BkYPUlm7HokkfhL7QXLVU9Twx2/jnvjI2w/rSgw1XaWKDHZpwa69I9SPUlUn9n/pIoYuPZ1vAt3xGoK3j/NretALAqF3Bwu529TA8PHfDKlAGE96Bs1TmmdPWU6qc8jlEP+QUlCsOA9dVe1tbG133tm2hEvIdjOUDpog0Kr+Ohyvxcm3i7HG1UF5sWy4svx7Bi1jG2t6Buks1Epw0O1oyVnrNE5WYOpt4DCzuLLFr9K1v6UW5OUGbs3UlJ8IL2N+4DC3BzxpOGRS4xn1SrkxOn3lx7IcWKrXzztq5aXIDzx70V9koZp9t+fKKlpchDuxU3zesTGKVRWM8Y9QyWxHjSY6+KLpnQPInxZoYVAKcwGiLJBSnHM/E3jgThGpt/MjdTjTtHX7Jq9MDRFErb9wIvElswsMZPn58nSt1Jt8Z7PMeAM/7NebWWFbuO7MRtWh2y/AOzKVwd3px0eRzsxDc8XoR3iIbFOdBTZNZUAN6+Ol7I1/pKTebbYirXnMJXd0Fkwd6EB4gMN08befWdvTINm75dgZKBZGP5XyDnpt5u07DgwxSmZEhctI7ydv1CJgxkkKg+sM/Z10CGVSlGi/kpW5r9FItK9o1nJQWTri9aZm+ugNixLbC8UXmGKF++H87TJPWCzRgVCoy0tkG+V1bmvQI= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: 931a5415-bd00-4a43-e811-08dabb284c66 X-MS-Exchange-CrossTenant-AuthSource: VI1PR0402MB3439.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2022 10:11:38.2182 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: +5CDPJHQyexQOBKv57FhsTQgkAFkKGEXWnLPX4cKl2xZkisuEIZcSLcTz+36Knhl X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB7261 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221031_031142_263944_CC801D66 X-CRM114-Status: GOOD ( 10.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add additional 500Mhz/800Mhz CSR clock ranges since NXP S32CC DWMAC can support higher frequencies. Signed-off-by: Jan Petrous Signed-off-by: Chester Lin --- drivers/net/ethernet/stmicro/stmmac/common.h | 2 ++ drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 4 ++++ include/linux/stmmac.h | 2 ++ 3 files changed, 8 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h index 6b5d96bced47..5b7e8cc70439 100644 --- a/drivers/net/ethernet/stmicro/stmmac/common.h +++ b/drivers/net/ethernet/stmicro/stmmac/common.h @@ -222,6 +222,8 @@ struct stmmac_safety_stats { #define CSR_F_150M 150000000 #define CSR_F_250M 250000000 #define CSR_F_300M 300000000 +#define CSR_F_500M 500000000 +#define CSR_F_800M 800000000 #define MAC_CSR_H_FRQ_MASK 0x20 diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 8273e6a175c8..68ac3680c04e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -323,6 +323,10 @@ static void stmmac_clk_csr_set(struct stmmac_priv *priv) priv->clk_csr = STMMAC_CSR_150_250M; else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M)) priv->clk_csr = STMMAC_CSR_250_300M; + else if ((clk_rate >= CSR_F_300M) && (clk_rate < CSR_F_500M)) + priv->clk_csr = STMMAC_CSR_300_500M; + else if ((clk_rate >= CSR_F_500M) && (clk_rate < CSR_F_800M)) + priv->clk_csr = STMMAC_CSR_500_800M; } if (priv->plat->has_sun8i) { diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index fb2e88614f5d..307980c808f7 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -34,6 +34,8 @@ #define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */ #define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */ #define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */ +#define STMMAC_CSR_300_500M 0x6 /* MDC = clk_scr_i/204 */ +#define STMMAC_CSR_500_800M 0x7 /* MDC = clk_scr_i/324 */ /* MTL algorithms identifiers */ #define MTL_TX_ALGORITHM_WRR 0x0