From patchwork Wed Nov 2 09:19:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 13027917 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EBF97C4332F for ; Wed, 2 Nov 2022 09:23:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=wCHOKTWOg/TX/KLoYyN2iQ2WP4nUn1gUFDE/klP1I0c=; b=rmqgcdH0JG8Yva ZkZTYmQFa+mTiML2B0laUtKam84Zi7P9KbczpHsG5f56sQ6kobpQxay/ozqDJzo535BoY2hUVjp3r NO5XyJgVJ4sjAZbYAsUUHhoo4Cr4U4EdHwD/TAlBYXwwKvvHnuar3mdnDCm/lvEkrsjM0XRCRU4eV ln2Z9kDtufNggHp8efqaTjow/MyBN/9oanlpIL2zg8N5Jck+Twp/eHhiQyzMmRxOrWXJG1Z7q2TCP gn13ViUdZIpzZi2OKLIakdQYOfcMG9+ahOh49CixX9Midlx8LU0XDfxQEGtC8bv5UpE6D+3Pb/6Mq F3LAYtFoAyZ6omNRmpfA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oq9xM-00ABsh-TE; Wed, 02 Nov 2022 09:22:45 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oq9vQ-00AANc-Bz for linux-arm-kernel@bombadil.infradead.org; Wed, 02 Nov 2022 09:20:44 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Type:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:CC:To:From:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=zSm/tCiWDz8IwwowFawgSF9n7YJ3Rhu0te7oRoRDPgw=; b=iJVuhaoosZMVnKyf/5AkdxRLbn Hubghb2vzNB6XeY7fZz0PVdPKMwltF9j9LZuA5N0UiGVniGQP5lvoxiSickL5KqPE5qknWkKjHLHA 8plVle6LBkmARdgQSsrWDPCi2sq5WHQG8QbJsKTdA8I/QBqkV3mjn3Nk2TrG3/t6vokrnGjRL5v5M IvoKB1+IiNo5EQnLaItba3lt3d5f9eCZC620Q/XwYDmHCW+ftTmFyJYcdWHIVxZ0cFb9kzr4lgKOC BBCU+WWTuNBf1hc8fMOLTcXPigN7ooIQ77Opp3FoWWdw9x2cGpZL9PDmm25EhRArvQaW+gDasuIhZ 1H8uQ2Og==; Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by desiato.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oq9vM-008M29-BO for linux-arm-kernel@lists.infradead.org; Wed, 02 Nov 2022 09:20:42 +0000 Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2A28FOJS004893; Wed, 2 Nov 2022 09:19:54 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=zSm/tCiWDz8IwwowFawgSF9n7YJ3Rhu0te7oRoRDPgw=; b=YaxiWWfXeSRQVopL2LVcbqiU2OT+s1y40o7uHGP+mHT3pBVaRU4JDwfZ3VxM6nd52MQ+ s+6LZ515Ky7o+Et/OAI96zz71TtYyFPzLxX9n356UbEDuiS+VfvqNCicWdBOemuGDSh+ FMKzfhRDdP1dHYUh8UnqQfGWknfK1AzDJVQ5Deet6JqN5ZCqqanXISFAmy1ZzbbNn8Oa DNaok2loTdw461RoBkT5opEl4w1j3pZ89qihHxitfxoorklNAaZFD4zvxiGeJt8/DVEq Vx+6JpAXAE7FYKyGgvIZoOwDwCPSIxrizNdoVKcWJ1jZ+TFRVrIFERLPnQQTejSNg164 Yg== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3kkja3gf2f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 02 Nov 2022 09:19:54 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2A29Jq9M010944 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 2 Nov 2022 09:19:52 GMT Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 2 Nov 2022 02:19:49 -0700 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach CC: Mao Jinlong , Leo Yan , "Greg Kroah-Hartman" , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Hao Zhang , , Bjorn Andersson Subject: [PATCH v14 4/9] coresight-tpdm: Add DSB dataset support Date: Wed, 2 Nov 2022 17:19:10 +0800 Message-ID: <20221102091915.15281-5-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221102091915.15281-1-quic_jinlmao@quicinc.com> References: <20221102091915.15281-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: -pgQWohd4zCSpZ9X5vsKPOqrp3siKGbH X-Proofpoint-GUID: -pgQWohd4zCSpZ9X5vsKPOqrp3siKGbH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-02_06,2022-11-01_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 bulkscore=0 adultscore=0 clxscore=1015 phishscore=0 mlxscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2211020055 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221102_092040_908239_F175EBD7 X-CRM114-Status: GOOD ( 22.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org TPDM serves as data collection component for various dataset types. DSB(Discrete Single Bit) is one of the dataset types. DSB subunit can be enabled for data collection by writing 1 to the first bit of DSB_CR register. This change is to add enable/disable function for DSB dataset by writing DSB_CR register. Reviewed-by: Suzuki K Poulose Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- drivers/hwtracing/coresight/coresight-tpdm.c | 56 ++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 22 ++++++++ 2 files changed, 78 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 6f9a136b2c3f..f6d653a45c99 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -20,7 +20,28 @@ DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm"); +static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) +{ + u32 val; + + /* Set the enable bit of DSB control register to 1 */ + val = readl_relaxed(drvdata->base + TPDM_DSB_CR); + val |= TPDM_DSB_CR_ENA; + writel_relaxed(val, drvdata->base + TPDM_DSB_CR); +} + /* TPDM enable operations */ +static void __tpdm_enable(struct tpdm_drvdata *drvdata) +{ + CS_UNLOCK(drvdata->base); + + /* Check if DSB datasets is present for TPDM. */ + if (drvdata->datasets & TPDM_PIDR0_DS_DSB) + tpdm_enable_dsb(drvdata); + + CS_LOCK(drvdata->base); +} + static int tpdm_enable(struct coresight_device *csdev, struct perf_event *event, u32 mode) { @@ -32,6 +53,7 @@ static int tpdm_enable(struct coresight_device *csdev, return -EBUSY; } + __tpdm_enable(drvdata); drvdata->enable = true; spin_unlock(&drvdata->spinlock); @@ -39,7 +61,28 @@ static int tpdm_enable(struct coresight_device *csdev, return 0; } +static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata) +{ + u32 val; + + /* Set the enable bit of DSB control register to 0 */ + val = readl_relaxed(drvdata->base + TPDM_DSB_CR); + val &= ~TPDM_DSB_CR_ENA; + writel_relaxed(val, drvdata->base + TPDM_DSB_CR); +} + /* TPDM disable operations */ +static void __tpdm_disable(struct tpdm_drvdata *drvdata) +{ + CS_UNLOCK(drvdata->base); + + /* Check if DSB datasets is present for TPDM. */ + if (drvdata->datasets & TPDM_PIDR0_DS_DSB) + tpdm_disable_dsb(drvdata); + + CS_LOCK(drvdata->base); +} + static void tpdm_disable(struct coresight_device *csdev, struct perf_event *event) { @@ -51,6 +94,7 @@ static void tpdm_disable(struct coresight_device *csdev, return; } + __tpdm_disable(drvdata); drvdata->enable = false; spin_unlock(&drvdata->spinlock); @@ -66,6 +110,17 @@ static const struct coresight_ops tpdm_cs_ops = { .source_ops = &tpdm_source_ops, }; +static void tpdm_init_default_data(struct tpdm_drvdata *drvdata) +{ + u32 pidr; + + CS_UNLOCK(drvdata->base); + /* Get the datasets present on the TPDM. */ + pidr = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0); + drvdata->datasets |= pidr & GENMASK(TPDM_DATASETS - 1, 0); + CS_LOCK(drvdata->base); +} + static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) { void __iomem *base; @@ -107,6 +162,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR(drvdata->csdev); spin_lock_init(&drvdata->spinlock); + tpdm_init_default_data(drvdata); /* Decrease pm refcount when probe is done.*/ pm_runtime_put(&adev->dev); diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index c87b982d963e..c8a101cbb4c7 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -6,6 +6,26 @@ #ifndef _CORESIGHT_CORESIGHT_TPDM_H #define _CORESIGHT_CORESIGHT_TPDM_H +/* The max number of the datasets that TPDM supports */ +#define TPDM_DATASETS 7 + +/* DSB Subunit Registers */ +#define TPDM_DSB_CR (0x780) +/* Enable bit for DSB subunit */ +#define TPDM_DSB_CR_ENA BIT(0) + +/** + * The bits of PERIPHIDR0 register. + * The fields [6:0] of PERIPHIDR0 are used to determine what + * interfaces and subunits are present on a given TPDM. + * + * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0 + * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0 + */ + +#define TPDM_PIDR0_DS_IMPDEF BIT(0) +#define TPDM_PIDR0_DS_DSB BIT(1) + /** * struct tpdm_drvdata - specifics associated to an TPDM component * @base: memory mapped base address for this component. @@ -13,6 +33,7 @@ * @csdev: component vitals needed by the framework. * @spinlock: lock for the drvdata value. * @enable: enable status of the component. + * @datasets: The datasets types present of the TPDM. */ struct tpdm_drvdata { @@ -21,6 +42,7 @@ struct tpdm_drvdata { struct coresight_device *csdev; spinlock_t spinlock; bool enable; + unsigned long datasets; }; #endif /* _CORESIGHT_CORESIGHT_TPDM_H */