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Wed, 02 Nov 2022 11:44:22 -0700 (PDT) Received: from eriador.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id t8-20020a05651c204800b00277092c03e7sm2277540ljo.33.2022.11.02.11.44.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 11:44:22 -0700 (PDT) From: Dmitry Baryshkov To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Rob Clark Cc: Vinod Koul , Sai Prakash Ranjan , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, freedreno@lists.freedesktop.org Subject: [RFC PATCH v2 01/11] arm64: dts: qcom: msm8996: change order of SMMU clocks on this platform Date: Wed, 2 Nov 2022 21:44:10 +0300 Message-Id: <20221102184420.534094-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221102184420.534094-1-dmitry.baryshkov@linaro.org> References: <20221102184420.534094-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221102_114424_995556_31FE7127 X-CRM114-Status: GOOD ( 11.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Change order of SMMU clocks to match the schema. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 31 +++++++++++++-------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index c0a2baffa49d..9331327678d8 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2205,9 +2205,9 @@ adreno_smmu: iommu@b40000 { ; #iommu-cells = <1>; - clocks = <&mmcc GPU_AHB_CLK>, - <&gcc GCC_MMSS_BIMC_GFX_CLK>; - clock-names = "iface", "bus"; + clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>, + <&mmcc GPU_AHB_CLK>; + clock-names = "bus", "iface"; power-domains = <&mmcc GPU_GDSC>; }; @@ -2272,9 +2272,9 @@ mdp_smmu: iommu@d00000 { , ; #iommu-cells = <1>; - clocks = <&mmcc SMMU_MDP_AHB_CLK>, - <&mmcc SMMU_MDP_AXI_CLK>; - clock-names = "iface", "bus"; + clocks = <&mmcc SMMU_MDP_AXI_CLK>, + <&mmcc SMMU_MDP_AHB_CLK>; + clock-names = "bus", "iface"; power-domains = <&mmcc MDSS_GDSC>; }; @@ -2292,9 +2292,9 @@ venus_smmu: iommu@d40000 { , ; power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; - clocks = <&mmcc SMMU_VIDEO_AHB_CLK>, - <&mmcc SMMU_VIDEO_AXI_CLK>; - clock-names = "iface", "bus"; + clocks = <&mmcc SMMU_VIDEO_AXI_CLK>, + <&mmcc SMMU_VIDEO_AHB_CLK>; + clock-names = "bus", "iface"; #iommu-cells = <1>; status = "okay"; }; @@ -2308,10 +2308,9 @@ vfe_smmu: iommu@da0000 { , ; power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; - clocks = <&mmcc SMMU_VFE_AHB_CLK>, - <&mmcc SMMU_VFE_AXI_CLK>; - clock-names = "iface", - "bus"; + clocks = <&mmcc SMMU_VFE_AXI_CLK>, + <&mmcc SMMU_VFE_AHB_CLK>; + clock-names = "bus", "iface"; #iommu-cells = <1>; }; @@ -2336,9 +2335,9 @@ lpass_q6_smmu: iommu@1600000 { , ; - clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>, - <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; - clock-names = "iface", "bus"; + clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>, + <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>; + clock-names = "bus", "iface"; }; slpi_pil: remoteproc@1c00000 {