| Message ID | 20221103044125.172864-5-mranostay@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | J721S2: Add support for additional IPs | expand |
On 03/11/22 10:11 am, Matt Ranostay wrote: > From: Aswath Govindraju <a-govindraju@ti.com> > > Configure first lane to PCIe, the second lane to USB and the last two lanes > to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is > connected to PCIe. > > Cc: Vignesh Raghavendra <vigneshr@ti.com> > Cc: Nishanth Menon <nm@ti.com> > Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> > Signed-off-by: Matt Ranostay <mranostay@ti.com> > --- > .../dts/ti/k3-j721s2-common-proc-board.dts | 22 +++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts > index a7aa6cf08acd..c3a397484c70 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts > @@ -9,6 +9,9 @@ > > #include "k3-j721s2-som-p0.dtsi" > #include <dt-bindings/net/ti-dp83867.h> > +#include <dt-bindings/phy/phy-cadence.h> > +#include <dt-bindings/phy/phy.h> > +#include <dt-bindings/mux/ti-serdes.h> > > / { > compatible = "ti,j721s2-evm", "ti,j721s2"; > @@ -296,6 +299,25 @@ &cpsw_port1 { > phy-handle = <&phy0>; > }; > > +&serdes_ln_ctrl { > + idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>, > + <J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>; > +}; > + > +&serdes_refclk { > + clock-frequency = <100000000>; > +}; > + > +&serdes0 { > + serdes0_pcie_link: phy@0 { > + reg = <0>; > + cdns,num-lanes = <1>; > + #phy-cells = <0>; > + cdns,phy-type = <PHY_TYPE_PCIE>; > + resets = <&serdes_wiz0 1>; > + }; > +}; > + > &mcu_mcan0 { > status = "okay"; > pinctrl-names = "default"; Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index a7aa6cf08acd..c3a397484c70 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -9,6 +9,9 @@ #include "k3-j721s2-som-p0.dtsi" #include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/phy/phy-cadence.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/mux/ti-serdes.h> / { compatible = "ti,j721s2-evm", "ti,j721s2"; @@ -296,6 +299,25 @@ &cpsw_port1 { phy-handle = <&phy0>; }; +&serdes_ln_ctrl { + idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>, + <J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>; +}; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&serdes0 { + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + resets = <&serdes_wiz0 1>; + }; +}; + &mcu_mcan0 { status = "okay"; pinctrl-names = "default";