| Message ID | 20221103044125.172864-9-mranostay@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | J721S2: Add support for additional IPs | expand |
On 03/11/22 10:11, Matt Ranostay wrote: > From: Aswath Govindraju <a-govindraju@ti.com> > > x1 lane PCIe slot in the common processor board is enabled and connected to > J721S2 SOM. Add PCIe DT node in common processor board to reflect the > same. > > Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> > Signed-off-by: Matt Ranostay <mranostay@ti.com> > --- > .../boot/dts/ti/k3-j721s2-common-proc-board.dts | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 0503e690cfaf..862611784ab3 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -374,6 +374,20 @@ flash@0{ }; }; +&pcie1_rc { + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + +&pcie1_ep { + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; + status = "disabled"; +}; + &mcu_mcan0 { status = "okay"; pinctrl-names = "default";