From patchwork Thu Nov 3 04:41:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Ranostay X-Patchwork-Id: 13029536 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E386C4332F for ; Thu, 3 Nov 2022 04:44:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=XcxUky6x1unp7zjYnJrWEwjfG522ZflRKl3scOUpLbA=; b=LXWK8q3q9i+Uo4 Y7P7gy2I67pNZZACh0Jq0mLfyI2YA9ambgsw4edwIqXcm0ESiV+kJsljT5A2pxM9EEQDh+j+ID+C2 dGQIhln3Z5m28d/UGOn36InBW12c8BjAn5XlTVqWIAOSZAPnOy9FelSxOmeIrZ62M/KvVIe5DJMtZ S8fKHmnLXAsi9/5ZQctEKqJXp0FUDzwuWLRVg5Okgw1H4ieZrUltygw0T/lPJlVEoSU0+PnSI+Jof XbDWSv8LSrh53XajxLXw57rUOgDQ8+CvQMaLMckL7YpG07RWR245EYNNfEKjCpabQF0POEcItziFn JJcHUlCcNzr6ziLVIchQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqS4k-00G1Wm-0f; Thu, 03 Nov 2022 04:43:34 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqS3m-00G0ib-SN for linux-arm-kernel@lists.infradead.org; Thu, 03 Nov 2022 04:42:36 +0000 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2A34gVtU060248; Wed, 2 Nov 2022 23:42:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1667450552; bh=2vWsXnJDtt3+RxVROIV3BAOZKS5Zl/tW4eoVo7lBOc4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=aqnllL8ShAWd5H/NI4OJaetzQcoj6zod0h4NodQ9T+bDl7iCf0msaelitizEe2kBj 2sypdDHdbjmVNVb3hkqn05rXBQw8gR1MI8jHf4yq1bLZF2Rfr2nSQoyAV1NUoqgQNz Z/DuqaVPeWIbgbka7Vx3eZEIarIm0KcT6sLpoDTY= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2A34gVYn081935 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 2 Nov 2022 23:42:31 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Wed, 2 Nov 2022 23:42:31 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 2 Nov 2022 23:42:31 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A34gQ4r053797; Wed, 2 Nov 2022 23:42:29 -0500 From: Matt Ranostay To: , , , , CC: , Subject: [PATCH v5 8/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe Date: Wed, 2 Nov 2022 21:41:25 -0700 Message-ID: <20221103044125.172864-9-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT In-Reply-To: <20221103044125.172864-1-mranostay@ti.com> References: <20221103044125.172864-1-mranostay@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221102_214234_984730_234D996F X-CRM114-Status: GOOD ( 10.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Aswath Govindraju x1 lane PCIe slot in the common processor board is enabled and connected to J721S2 SOM. Add PCIe DT node in common processor board to reflect the same. Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Signed-off-by: Matt Ranostay Reviewed-by: Siddharth Vadapalli --- .../boot/dts/ti/k3-j721s2-common-proc-board.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 0503e690cfaf..862611784ab3 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -374,6 +374,20 @@ flash@0{ }; }; +&pcie1_rc { + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + +&pcie1_ep { + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; + status = "disabled"; +}; + &mcu_mcan0 { status = "okay"; pinctrl-names = "default";