From patchwork Fri Nov 4 06:03:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13031379 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 434CDC4332F for ; Fri, 4 Nov 2022 06:04:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TkD60WePL77hLmsHv7uMGQDcoA9Slha8Bo9VGkyCUsc=; b=KFu0IuiClxjLEc ZBOzX0Ty9Q+w+1bdXKcvu2y6E9FKomVVBKWT8g3EP72Ypk+Ftt5ZSSG2/1jCdSqhCDysUyNFSw5Db rA9nSd+TFnP41XT7dxzRU4zR97T3a58QyvSufH7ZoGKnvH/AQn9vXjVTckR8RcGxjgVEInZQlTFW4 XS8uFEncREeNJL3ZNfVt5pJwhAV0oyK6yj9Bo2I+tq3RxgKBfVk9Jl1rB6XhkYbF4TPYBPO1ic3Z+ hCXg7iTVrWUHc6+cWlcCNlxORJ1c6nOWMjg2h1N/zXm4wSUvEIg2G2ujSMHeXAmaHtN46E+52K5hq AYFY0h+e0yO82cZ+7OrQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqpnb-002TXM-Vb; Fri, 04 Nov 2022 06:03:28 +0000 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqpnR-002TT1-Pn for linux-arm-kernel@lists.infradead.org; Fri, 04 Nov 2022 06:03:19 +0000 Received: by mail-pl1-x62e.google.com with SMTP id k7so3990487pll.6 for ; Thu, 03 Nov 2022 23:03:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IASNZHNwvbWHeDpezdCT15D5MRNvDyxMNfFoWg+ExSg=; b=aqcZP+ExcDnuxlJ8XnJBEdobJerBZCyEDR6WgadSMDtxAT5rQDMB7pSrN/SEN7g5gn rxCauaz72JTCG0XXuxBLWk8Lma1OtRHbiSFJIWyAItitHSQ0SjasMTod0dUyRtPSCfqh J2DQk6/1ApW+OHwZW7CbEVbXZ6yuSdrG29XQ2mCmXp85H9rPN9Yp9umUa65ZsQa3dMRg 7csvZDxOHLVrb9mzDtliGNFLwHS3qZpwMFtXK1mJiDMhvn1OLUPhYiYf6CGsHWAYwrft 8BGZsOUF5kbYjlISj9q+Vr1MWcTjrJ1kohGMQbfwGz7Qp+r/ojuMkhtJjINqjc02mZFE shqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IASNZHNwvbWHeDpezdCT15D5MRNvDyxMNfFoWg+ExSg=; b=5fJgTDb6i3rCHUPdGq1dyG6SbrpSjnOfTAMmoY0TQU/gYiQvZc85Acgv3SrQEIgnfV aTFZdQvWNMgA4mka628t5jNJZ++KXhlXp1kVj3oFfq5glf4YguiTHYaBKbHErM4t/nsI 6socCCeaFiykUpOZNlJAkXh49u0XR9uo54hAzFjZpmwov4+eODUCcDtn82MP/0+bA4r5 c16JJwmEIxoWVqe7pishW/o+bAjS1t6Mt9pW2ixf7NTj0x6u2JWdDaGBSk2TxT+XcWxU lwDgy44uv+AmZijmrJ2a8TmkhBUIpYIlnoMwfJsfUSu8F0O1gWUsoKZRl/GSia3031yO ch6g== X-Gm-Message-State: ACrzQf2ZRZYyr2504b89IySWq5mn5LIiBWUXANmdGMVA/U2imEI7Y+XZ pINJpSxXxJHKIpqNvYnxb1FsSg== X-Google-Smtp-Source: AMsMyM4BZ8e1+Z6CWv7xo7n9Xdqu0AV/B3q7MOVKIKzutmdF3cgTx+c+aeb/bgUOUcHCCggYF0spEQ== X-Received: by 2002:a17:902:e891:b0:186:c544:8b1e with SMTP id w17-20020a170902e89100b00186c5448b1emr33359635plg.163.1667541797453; Thu, 03 Nov 2022 23:03:17 -0700 (PDT) Received: from archlinux.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id f15-20020a170902684f00b00186bc66d2cbsm1727180pln.73.2022.11.03.23.03.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Nov 2022 23:03:17 -0700 (PDT) From: Andy Chiu To: davem@davemloft.net, andrew@lunn.ch, kuba@kernel.org, michal.simek@xilinx.com, radhey.shyam.pandey@xilinx.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, pabeni@redhat.com, edumazet@google.com, andy.chiu@sifive.com, greentime.hu@sifive.com Subject: [PATCH v3 net-next 2/3] net: axienet: set mdio clock according to bus-frequency Date: Fri, 4 Nov 2022 14:03:04 +0800 Message-Id: <20221104060305.1025215-3-andy.chiu@sifive.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20221104060305.1025215-1-andy.chiu@sifive.com> References: <20221104060305.1025215-1-andy.chiu@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221103_230317_876058_3853F5B1 X-CRM114-Status: GOOD ( 19.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Some FPGA platforms have 80KHz MDIO bus frequency constraint when connecting Ethernet to its on-board external Marvell PHY. Thus, we may have to set MDIO clock according to the DT. Otherwise, use the default 2.5 MHz, as specified by 802.3, if the entry is not present. Signed-off-by: Andy Chiu Reviewed-by: Greentime Hu --- .../net/ethernet/xilinx/xilinx_axienet_mdio.c | 46 +++++++++++++------ 1 file changed, 32 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c index e1f51a071888..5e1619ce8074 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c @@ -147,15 +147,18 @@ static int axienet_mdio_write(struct mii_bus *bus, int phy_id, int reg, /** * axienet_mdio_enable - MDIO hardware setup function * @lp: Pointer to axienet local data structure. + * @np: Pointer to mdio device tree node. * * Return: 0 on success, -ETIMEDOUT on a timeout. * * Sets up the MDIO interface by initializing the MDIO clock and enabling the * MDIO interface in hardware. **/ -static int axienet_mdio_enable(struct axienet_local *lp) +static int axienet_mdio_enable(struct axienet_local *lp, struct device_node *np) { + u32 mdio_freq = MAX_MDIO_FREQ; u32 host_clock; + u32 clk_div; lp->mii_clk_div = 0; @@ -184,6 +187,12 @@ static int axienet_mdio_enable(struct axienet_local *lp) host_clock); } + if (np) + of_property_read_u32(np, "clock-frequency", &mdio_freq); + if (mdio_freq != MAX_MDIO_FREQ) + netdev_info(lp->ndev, "Setting non-standard mdio bus frequency to %u Hz\n", + mdio_freq); + /* clk_div can be calculated by deriving it from the equation: * fMDIO = fHOST / ((1 + clk_div) * 2) * @@ -209,13 +218,20 @@ static int axienet_mdio_enable(struct axienet_local *lp) * "clock-frequency" from the CPU */ - lp->mii_clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1; + clk_div = (host_clock / (mdio_freq * 2)) - 1; /* If there is any remainder from the division of - * fHOST / (MAX_MDIO_FREQ * 2), then we need to add + * fHOST / (mdio_freq * 2), then we need to add * 1 to the clock divisor or we will surely be above 2.5 MHz */ - if (host_clock % (MAX_MDIO_FREQ * 2)) - lp->mii_clk_div++; + if (host_clock % (mdio_freq * 2)) + clk_div++; + + /* Check for overflow of mii_clk_div */ + if (clk_div & ~XAE_MDIO_MC_CLOCK_DIVIDE_MAX) { + netdev_warn(lp->ndev, "MDIO clock divisor overflow\n"); + return -EOVERFLOW; + } + lp->mii_clk_div = (u8)clk_div; netdev_dbg(lp->ndev, "Setting MDIO clock divisor to %u/%u Hz host clock.\n", @@ -242,10 +258,6 @@ int axienet_mdio_setup(struct axienet_local *lp) struct mii_bus *bus; int ret; - ret = axienet_mdio_enable(lp); - if (ret < 0) - return ret; - bus = mdiobus_alloc(); if (!bus) return -ENOMEM; @@ -261,15 +273,21 @@ int axienet_mdio_setup(struct axienet_local *lp) lp->mii_bus = bus; mdio_node = of_get_child_by_name(lp->dev->of_node, "mdio"); + ret = axienet_mdio_enable(lp, mdio_node); + if (ret < 0) + goto unregister; ret = of_mdiobus_register(bus, mdio_node); + if (ret) + goto unregister; of_node_put(mdio_node); - if (ret) { - mdiobus_free(bus); - lp->mii_bus = NULL; - return ret; - } axienet_mdio_mdc_disable(lp); return 0; + +unregister: + of_node_put(mdio_node); + mdiobus_free(bus); + lp->mii_bus = NULL; + return ret; } /**