From patchwork Fri Nov 4 08:01:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 13031503 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7099BC433FE for ; Fri, 4 Nov 2022 08:03:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=aE8+10FhG2QhgcPDoEC7xU+yegZwFax39ClZ5c1mrbQ=; b=pVYlGip4/SGyYp kYMeNl5Y0mKPYij4LElkCN/90h+0OEVgLqHkNexSLG2KFCxs15rcKyv4Hnq/OgWm7Ll/Cd7MUGUCW GYYatGIHGNP4OyNY7hSRxwXDv9bw5e2All4Ld98qeAKe5DP+W4wc50ihl8i93KpxgmG1/iwUrnmBG 7QFWYNM1px4eBi6geNhEDrRdo8r/RT4KbYxx36DmpDOWrxu3YsKvKaVfxAFrNEngJ6TiFR7u3sJMF t4wjHlw3HQgisgDXaDaHxQMP0mrz12qEKgIP095azTdFqzEQz8bfb/+U7RifM04cbxoXvSlbxUrpv 3LPfTW/lNN6K2sFDIMsg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqrea-002qke-Da; Fri, 04 Nov 2022 08:02:16 +0000 Received: from muru.com ([72.249.23.125]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqre2-002qaV-5R for linux-arm-kernel@lists.infradead.org; Fri, 04 Nov 2022 08:01:45 +0000 Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id E5D0C8171; Fri, 4 Nov 2022 07:51:58 +0000 (UTC) From: Tony Lindgren To: Nishanth Menon , Vignesh Raghavendra Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Keerthy , Georgi Vlaev Subject: [PATCH 2/4] arm64: dts: ti: k3-am65: Add general purpose timers for am65 Date: Fri, 4 Nov 2022 10:01:20 +0200 Message-Id: <20221104080122.49220-3-tony@atomide.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221104080122.49220-1-tony@atomide.com> References: <20221104080122.49220-1-tony@atomide.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221104_010142_281258_2EF4AA0F X-CRM114-Status: GOOD ( 14.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org There are 12 general purpose timers on am65 that can be used for things like PWM using pwm-omap-dmtimer driver. There are also additional four timers in the MCU domain that do not have interrupts routable for Linux. We configure the timers with the 25 MHz input clock by default as the 32.768 kHz clock may not be wired on the device. We leave the MCU domain timers clock mux unconfigured, and mark the MCU domain timers reserved. The MCU domain timers are likely reserved by the software for the ESM module. Compared to am64, the timer clocks are different on am65. And the MCU timers are at a different IO address. Then j72 adds more timers compared to am65 with a total of 30 timers. And the j72 clocks are different. To avoid duplication for dtsi files, eventually we may want to consider adding timer specific shared dtsi files with the timer clocks mapped using SoC specific files in include/dt-bindings/clock. But let's get am65 timers usable first. Cc: Keerthy Cc: Nishanth Menon Cc: Vignesh Raghavendra Signed-off-by: Tony Lindgren --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 144 +++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 45 +++++++ 2 files changed, 189 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -272,6 +272,150 @@ main_spi4: spi@2140000 { #size-cells = <0>; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 23 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 23 0>; + assigned-clock-parents = <&k3_clks 23 1>; + power-domains = <&k3_pds 23 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 24 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 24 0>; + assigned-clock-parents = <&k3_clks 24 1>; + power-domains = <&k3_pds 24 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 27 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 27 0>; + assigned-clock-parents = <&k3_clks 27 1>; + power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 28 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 28 0>; + assigned-clock-parents = <&k3_clks 28 1>; + power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 29 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 29 0>; + assigned-clock-parents = <&k3_clks 29 1>; + power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 30 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 30 0>; + assigned-clock-parents = <&k3_clks 30 1>; + power-domains = <&k3_pds 30 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 31 0>; + assigned-clocks = <&k3_clks 31 0>; + assigned-clock-parents = <&k3_clks 31 1>; + clock-names = "fck"; + power-domains = <&k3_pds 31 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 32 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 32 0>; + assigned-clock-parents = <&k3_clks 32 1>; + power-domains = <&k3_pds 32 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer8: timer@2480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 33 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 33 0>; + assigned-clock-parents = <&k3_clks 33 1>; + power-domains = <&k3_pds 33 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer9: timer@2490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 34 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 34 0>; + assigned-clock-parents = <&k3_clks 34 1>; + power-domains = <&k3_pds 34 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer10: timer@24a0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24a0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 25 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 25 0>; + assigned-clock-parents = <&k3_clks 25 1>; + power-domains = <&k3_pds 25 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer11: timer@24b0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24b0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 26 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 26 0>; + assigned-clock-parents = <&k3_clks 26 1>; + power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + sdhci0: mmc@4f80000 { compatible = "ti,am654-sdhci-5.1"; reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -132,6 +132,51 @@ adc { }; }; + /* + * The MCU domain timer interrupts are routed only to the ESM module, + * and not currently available for Linux. The MCU domain timers are + * of limited use without interrupts, and likely reserved by the ESM. + */ + mcu_timer0: timer@40400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40400000 0x00 0x400>; + clocks = <&k3_clks 35 0>; + clock-names = "fck"; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer1: timer@40410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40410000 0x00 0x400>; + clocks = <&k3_clks 36 0>; + clock-names = "fck"; + power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer2: timer@40420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40420000 0x00 0x400>; + clocks = <&k3_clks 37 0>; + clock-names = "fck"; + power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer3: timer@40430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40430000 0x00 0x400>; + clocks = <&k3_clks 38 0>; + clock-names = "fck"; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + mcu_navss: bus@28380000 { compatible = "simple-mfd"; #address-cells = <2>;