From patchwork Tue Nov 8 04:13:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13035828 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 94CEBC4332F for ; Tue, 8 Nov 2022 04:16:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=r29vMNh7lT+FbyxtKgSDYyH4DhczsNnj07vWlyGPYv4=; b=pifnOGl1iMntMG CmmgTf74IP0xUCK6h41gaIDnHDKrKbgTkGUWJNZcOO7RVVcIEdwU92xGQdnbeZ1eClG/AXlymqeN5 1+u1Q6vrwkMA5DIQCNdafy7wu7Fm8Z0Rt8RagV8mWRyqpRUh6KraKS5TDxm8ooUh2ucJ1Q0GPT8BA 1Ef+bv8dZf8U7hwT/yUD0PzTmV4muCbR1oeJGjoTqX5Dit+w61FSD7XXihspSF8lMj/xToy4TRONH F/asQTt0OTB9kgiMXMKVwTfjDd4gpGgjXEbgsPJegTHT/munmyVpzlmL1j6DK7S3hqWQ9foChWb0S KgVyEUqCvsMX2EtlkVTg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1osG1U-002aqc-5e; Tue, 08 Nov 2022 04:15:40 +0000 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1osG0t-002aU1-Mz for linux-arm-kernel@lists.infradead.org; Tue, 08 Nov 2022 04:15:07 +0000 Received: by mail-pl1-x634.google.com with SMTP id l2so13066720pld.13 for ; Mon, 07 Nov 2022 20:15:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=edgeble-ai.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u8AupBO7ArfsThYZ4F3jhut22sgUXTSHnSRij7H265o=; b=Z0zqCeISHuhuSD/Z0K1gipY/JTZEs0knMG8OVc+G7PYWuJ464GtgOSQcZ4Urb0PZSS cxQbdIMHb5p7IDI3TGiXMtY4mcOSd9HXGXDUoSqLLEHMBxljc/jN68dfnF+T9K3B6wfr MKUKkBl4DOgW8fQc7gtM6xYgg08rh606h+6zVdbJj3jjmUyakS013aB+WJdkpwHE8LCU dNnD/voVDUVQ1Xl9R7wlputBqomfmr+2gEQ2DRQNySxCca3F8UEXV0LcolSQ1aaNyeTe 8RKfjqe7gmpVmxP6EspjWPd9yIvVOvuj7SSCBriA4kOWIsteNJYomZlc0rdfPwA4adg3 Oe4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u8AupBO7ArfsThYZ4F3jhut22sgUXTSHnSRij7H265o=; b=dYRBCRfATYHVSaoVmhCMDftBh+nVOiOliiq1zQXQYvHhGMGJ6A38RP1mvzb0norYZV UFK7kTJDyFIoiOl3bR7/VAtC0MPGpWL0EkkIN4PCZVmE4mbi5TSWqKuvbZFz90tYetVw 1izTxzC2XqIRWVz+FDn7sVFckkwpJ8JIdrV7W9qOFz0U0EfbSahKPhw+pNhHkLOYyG/7 NzJcmLsXn911Tj+EAMyaOpNYZhQaS99I64sXMwxocv0oSDAMOvNItrg9VZq+DRHg4dhK JrXjcwhXfN8Nh20oyqiGqwf9aOR50PKalnUTaX9IIcsa6Wa+v3TUymqdm9JUvoPdulJx EeFg== X-Gm-Message-State: ACrzQf0BCBs+azsdXIWoEnShupr4WjH5JC99hcDXcpopI6Q5RyoFMt89 xu2FgYTUuJhvYN5ih67CbqVvjQ== X-Google-Smtp-Source: AMsMyM57mOu2cJHtkfCwvWT27HoYaS1v11oVrytwy8uNPnTPpNMSS70eVV3rF74CttyFGXW9qcOCJQ== X-Received: by 2002:a17:90b:3594:b0:213:bf67:4d50 with SMTP id mm20-20020a17090b359400b00213bf674d50mr52403215pjb.32.1667880901522; Mon, 07 Nov 2022 20:15:01 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a809:63d1:2564:ea55:4e97]) by smtp.gmail.com with ESMTPSA id e5-20020a170902b78500b00186ac812ab0sm5799783pls.83.2022.11.07.20.14.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Nov 2022 20:15:01 -0800 (PST) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, Johan Jonker , Jagan Teki Subject: [PATCH v7 05/10] ARM: dts: rockchip: Add Rockchip RV1126 pinctrl Date: Tue, 8 Nov 2022 09:43:55 +0530 Message-Id: <20221108041400.157052-6-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221108041400.157052-1-jagan@edgeble.ai> References: <20221108041400.157052-1-jagan@edgeble.ai> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221107_201503_828900_68AADC9A X-CRM114-Status: GOOD ( 18.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add pinctrl definitions for Rockchip RV1126. From RK3568 on-wards pinctrl configurations are maintained in common conf file rockchip-pinconf.dtsi and it is available in arm64 path (arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi). So, include the same conf file to RV1126 pinctrl from arm64 path. Signed-off-by: Jagan Teki --- Changes for v7: - remove Edegble in license text Changes for v6: - updated commit message Changes for v5: - none Changes for v4: - update i2c pins - rebase on -next Changes for v3: - none Changes for v2: - spilt pinctrl as separate patch MAINTAINERS | 2 +- arch/arm/boot/dts/rv1126-pinctrl.dtsi | 211 ++++++++++++++++++++++++++ 2 files changed, 212 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/rv1126-pinctrl.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 5f66378dcfb0..4fd0fa773209 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2750,7 +2750,7 @@ F: Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml F: Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml F: Documentation/devicetree/bindings/spi/spi-rockchip.yaml F: arch/arm/boot/dts/rk3* -F: arch/arm/boot/dts/rv1108* +F: arch/arm/boot/dts/rv11* F: arch/arm/mach-rockchip/ F: drivers/*/*/*rockchip* F: drivers/*/*rockchip* diff --git a/arch/arm/boot/dts/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rv1126-pinctrl.dtsi new file mode 100644 index 000000000000..4bc419cc1210 --- /dev/null +++ b/arch/arm/boot/dts/rv1126-pinctrl.dtsi @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include +#include + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <1 RK_PA3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <0 RK_PC5 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <0 RK_PC6 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <0 RK_PC7 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <0 RK_PD0 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <0 RK_PD1 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <0 RK_PD2 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <0 RK_PD3 2 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clko */ + <0 RK_PD7 2 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>; + }; + }; + i2c0 { + /omit-if-no-ref/ + i2c0_xfer: i2c0-xfer { + rockchip,pins = + /* i2c0_scl */ + <0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>, + /* i2c0_sda */ + <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>; + }; + }; + sdmmc0 { + /omit-if-no-ref/ + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + /* sdmmc0_d0 */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d1 */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d2 */ + <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d3 */ + <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + /* sdmmc0_clk */ + <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + /* sdmmc0_cmd */ + <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_det: sdmmc0-det { + rockchip,pins = + <0 RK_PA3 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sdmmc0_pwr: sdmmc0-pwr { + rockchip,pins = + <0 RK_PC0 1 &pcfg_pull_none>; + }; + }; + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d1 */ + <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d2 */ + <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d3 */ + <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + /* sdmmc1_clk */ + <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + /* sdmmc1_cmd */ + <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_det: sdmmc1-det { + rockchip,pins = + <1 RK_PD0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sdmmc1_pwr: sdmmc1-pwr { + rockchip,pins = + <1 RK_PD1 2 &pcfg_pull_none>; + }; + }; + uart0 { + /omit-if-no-ref/ + uart0_xfer: uart0-xfer { + rockchip,pins = + /* uart0_rx */ + <1 RK_PC2 1 &pcfg_pull_up>, + /* uart0_tx */ + <1 RK_PC3 1 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + uart0_ctsn: uart0-ctsn { + rockchip,pins = + <1 RK_PC1 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart0_rtsn: uart0-rtsn { + rockchip,pins = + <1 RK_PC0 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart0_rtsn_gpio: uart0-rts-pin { + rockchip,pins = + <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rx_m0 */ + <0 RK_PB7 2 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <0 RK_PB6 2 &pcfg_pull_up>; + }; + }; + uart2 { + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rx_m1 */ + <3 RK_PA3 1 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <3 RK_PA2 1 &pcfg_pull_up>; + }; + }; + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rx_m0 */ + <3 RK_PC7 4 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <3 RK_PC6 4 &pcfg_pull_up>; + }; + }; + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + /* uart4_rx_m0 */ + <3 RK_PA5 4 &pcfg_pull_up>, + /* uart4_tx_m0 */ + <3 RK_PA4 4 &pcfg_pull_up>; + }; + }; + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rx_m0 */ + <3 RK_PA7 4 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <3 RK_PA6 4 &pcfg_pull_up>; + }; + }; +};