From patchwork Thu Nov 17 03:47:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13046077 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 51A22C4332F for ; Thu, 17 Nov 2022 03:49:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qclSdvlLXwU0i+5hdtvTHIfBLxhjfCaLtpe1KyVabvU=; b=4I7iro3QKOecPG DbTpVwCum8/9d4MCRAOxg2BWUM3jvlI7MJoS01xwv4RX6R6DpmFxop27FxvunAUUuv2xirAreKoe3 L/zBzjYnH3bdtB1Dm/UBvIOi0oqretZwXTKwqb9JnKmEoaZH3yASFbZOZLOgeMHbdbsHdv3tOQG7q UEG5E0IaPI0r7otTWV3l2aOIBIIVR9e2YcpGZlorZCnjUYNeNnRq56B36uK0r0IqQR6v6iyFdoC0f zfgP5jsvGk7vuc0MzZglIeQjNHmbJKG3whlWOLSqdPxos2bQXY3XeKYfmVuLCX9/RSDLqbRzah91T 7VEZ55cFKLx25hUlzeLQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ovVsy-009uM1-3W; Thu, 17 Nov 2022 03:48:20 +0000 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ovVsl-009uJU-1q for linux-arm-kernel@lists.infradead.org; Thu, 17 Nov 2022 03:48:08 +0000 Received: by mail-pf1-x433.google.com with SMTP id b29so527568pfp.13 for ; Wed, 16 Nov 2022 19:48:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qe8YO2bYKcCk4mjdRa7k4fBiBoq1F5abtOZtL0+7RAg=; b=ZlXqcQ/TBcjMH7qlWaregji379qaz3S+jNP56u2x3vrqT0XmJ6Lc3mIya/6A9Ly7kq tx+RTq3WurM26yQrDPjvTpAf/yeG9LY/0lehBQZ18/x1YrU9sgT5SG5qOTxuJsrRkplT 1d0xwf37vV67kF08KYsBHtpY+qgVOIygwdxtOM61WTMVp29/k0697XwGgKoDAgOAL+Ht d+ek8q7fdU0KPbVPZryptWZdYs9JjeVhhXfdw5ymX1K/LBX8SQhgquyL30fB7vcslUjT thP6tQCBUPcTOe+t0K06NDTTvW7S6zj5dF2QFqea2B1gxVmnponzvwBQ6P7FutJZruV4 ctCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qe8YO2bYKcCk4mjdRa7k4fBiBoq1F5abtOZtL0+7RAg=; b=vl4wslGR5w6e6KzNMxCHZXpMsnizjlb91lLKXYzAkF+jl762zWne+oa93/IJQmrayJ o8B+3Q1agCL6aO/mN4HwWoZMuBXsRoLNBsqHvIgxZvVbXQdqr4nzmpnO/NgSebmTBGqJ TnVTzllg+gppwOfle+Nu5K0gmopRyac6sPKDYTmAQ35/AcUDMiOEIwohBySXdWtUo0fm DkZBQaxjhLN7LA1TSZXQ9ZBIq9+/gmVyGZFpQyqTS74AuB1dplYmuFYohqp0ZZC7hT6e iRNU5PtMd0gK6WlJY/ksHxBfaYs1BqgXLZ+7peEIuYwqIOYAGnmgEdpO8X1mXjvpnSHn s/XA== X-Gm-Message-State: ANoB5pmaX0ThPzGLu8TYxHyVRtVI8q3aE/ni1QIhqCBQynjdqGCYVnzH ngXwImIzRiq1Y82Hb6YqjM389g== X-Google-Smtp-Source: AA0mqf5iz5cLKFk9oFqB7sAINpOlLMWPUNudtyaYnxyF7/W2Lzos3BsbDwOWnvh0z9i4I4oe4PXd7Q== X-Received: by 2002:a63:d908:0:b0:45f:fc05:270b with SMTP id r8-20020a63d908000000b0045ffc05270bmr470095pgg.14.1668656885320; Wed, 16 Nov 2022 19:48:05 -0800 (PST) Received: from archlinux.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id p22-20020a1709027ed600b00187197c499asm13016723plb.164.2022.11.16.19.48.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 19:48:04 -0800 (PST) From: Andy Chiu To: davem@davemloft.net, andrew@lunn.ch, kuba@kernel.org, michal.simek@xilinx.com, radhey.shyam.pandey@xilinx.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, pabeni@redhat.com, edumazet@google.com, andy.chiu@sifive.com, greentime.hu@sifive.com Subject: [PATCH v4 net-next 2/3] net: axienet: set mdio clock according to bus-frequency Date: Thu, 17 Nov 2022 11:47:50 +0800 Message-Id: <20221117034751.1347105-3-andy.chiu@sifive.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20221117034751.1347105-1-andy.chiu@sifive.com> References: <20221117034751.1347105-1-andy.chiu@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221116_194807_117618_152E340C X-CRM114-Status: GOOD ( 20.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Some FPGA platforms have 80KHz MDIO bus frequency constraint when connecting Ethernet to its on-board external Marvell PHY. Thus, we may have to set MDIO clock according to the DT. Otherwise, use the default 2.5 MHz, as specified by 802.3, if the entry is not present. Also, change MAX_MDIO_FREQ to DEFAULT_MDIO_FREQ because we may actually set MDIO bus frequency higher than 2.5MHz if undelying devices support it. Signed-off-by: Andy Chiu Reviewed-by: Greentime Hu Reviewed-by: Andrew Lunn --- .../net/ethernet/xilinx/xilinx_axienet_mdio.c | 48 +++++++++++++------ 1 file changed, 33 insertions(+), 15 deletions(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c index e1f51a071888..789a90997f4b 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c @@ -17,7 +17,7 @@ #include "xilinx_axienet.h" -#define MAX_MDIO_FREQ 2500000 /* 2.5 MHz */ +#define DEFAULT_MDIO_FREQ 2500000 /* 2.5 MHz */ #define DEFAULT_HOST_CLOCK 150000000 /* 150 MHz */ /* Wait till MDIO interface is ready to accept a new transaction.*/ @@ -147,15 +147,18 @@ static int axienet_mdio_write(struct mii_bus *bus, int phy_id, int reg, /** * axienet_mdio_enable - MDIO hardware setup function * @lp: Pointer to axienet local data structure. + * @np: Pointer to mdio device tree node. * * Return: 0 on success, -ETIMEDOUT on a timeout. * * Sets up the MDIO interface by initializing the MDIO clock and enabling the * MDIO interface in hardware. **/ -static int axienet_mdio_enable(struct axienet_local *lp) +static int axienet_mdio_enable(struct axienet_local *lp, struct device_node *np) { + u32 mdio_freq = DEFAULT_MDIO_FREQ; u32 host_clock; + u32 clk_div; lp->mii_clk_div = 0; @@ -184,6 +187,12 @@ static int axienet_mdio_enable(struct axienet_local *lp) host_clock); } + if (np) + of_property_read_u32(np, "clock-frequency", &mdio_freq); + if (mdio_freq != DEFAULT_MDIO_FREQ) + netdev_info(lp->ndev, "Setting non-standard mdio bus frequency to %u Hz\n", + mdio_freq); + /* clk_div can be calculated by deriving it from the equation: * fMDIO = fHOST / ((1 + clk_div) * 2) * @@ -209,13 +218,20 @@ static int axienet_mdio_enable(struct axienet_local *lp) * "clock-frequency" from the CPU */ - lp->mii_clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1; + clk_div = (host_clock / (mdio_freq * 2)) - 1; /* If there is any remainder from the division of - * fHOST / (MAX_MDIO_FREQ * 2), then we need to add + * fHOST / (mdio_freq * 2), then we need to add * 1 to the clock divisor or we will surely be above 2.5 MHz */ - if (host_clock % (MAX_MDIO_FREQ * 2)) - lp->mii_clk_div++; + if (host_clock % (mdio_freq * 2)) + clk_div++; + + /* Check for overflow of mii_clk_div */ + if (clk_div & ~XAE_MDIO_MC_CLOCK_DIVIDE_MAX) { + netdev_warn(lp->ndev, "MDIO clock divisor overflow\n"); + return -EOVERFLOW; + } + lp->mii_clk_div = (u8)clk_div; netdev_dbg(lp->ndev, "Setting MDIO clock divisor to %u/%u Hz host clock.\n", @@ -242,10 +258,6 @@ int axienet_mdio_setup(struct axienet_local *lp) struct mii_bus *bus; int ret; - ret = axienet_mdio_enable(lp); - if (ret < 0) - return ret; - bus = mdiobus_alloc(); if (!bus) return -ENOMEM; @@ -261,15 +273,21 @@ int axienet_mdio_setup(struct axienet_local *lp) lp->mii_bus = bus; mdio_node = of_get_child_by_name(lp->dev->of_node, "mdio"); + ret = axienet_mdio_enable(lp, mdio_node); + if (ret < 0) + goto unregister; ret = of_mdiobus_register(bus, mdio_node); + if (ret) + goto unregister; of_node_put(mdio_node); - if (ret) { - mdiobus_free(bus); - lp->mii_bus = NULL; - return ret; - } axienet_mdio_mdc_disable(lp); return 0; + +unregister: + of_node_put(mdio_node); + mdiobus_free(bus); + lp->mii_bus = NULL; + return ret; } /**