From patchwork Thu Nov 17 10:52:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13046590 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 27861C4332F for ; Thu, 17 Nov 2022 11:01:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=3Cg2WFE9w4U8LLIACRpEw+ohWyu0pQV+Krbe2mGUVpM=; b=erjsh4AUIr84+E kS2VwNWxnttG6x8vvbneQQhhZTL/zkSQtFdQoAWE4/YGxwBjD4pLJJk5XI2YFBE5OT9aqi+9B7rSU e9VWC6b4yw6EPZjSrPaaao2NOLoQyg4QUDrIkZpQYNCl8IEH0tbnA0/2oy2yZqKv8iXrRKy2jfWiD ZL8QGs7pByL98GblRbVweS4rxH6J6XRzgNyqQHnagBjGQ2jovSGbxSgvjYcnHQGbhnU8s67pO/lc1 Shuh4eYGyzcHc/KMYGAza70l4AINPdGiVp78yciTeWwEJlZpzFriBpYmm+sIniq9E9brBkAuzCM1Z SKB3qKtJI/yibT8NzRqg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ovcdL-00CsdY-Sz; Thu, 17 Nov 2022 11:00:40 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ovcWA-00CoK0-A1; Thu, 17 Nov 2022 10:53:16 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1668682395; x=1700218395; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=V+B/oow35dGgcpcT99slHtwXN+81/1x8fB2BGyRH3ZM=; b=QnjSob1C3mQr1QJbIXfjZxb4q7AueEfxdjwmKIjk6jRaHSuv31uR5KDf KpYV0dkQapU14fDKwpNc0A41JsusQ/oZ4enpbJN+xGjqUVukrLmTV92PQ cEGWvdbTp2qLCHd78RK4qB8/65xJ0y8lUScWnJ1stg2pOM171BWund4Ud FZrAHf1tOVaML4bWe+LWMOiEnO9mdloLXbabB8KbnbEMYtsWt7Ijlmyn5 aQSBeOmn8L+DttRGRrIh0FeR2CWPA9NbRH06VTh2YBvhJ4Od6JY99hv7n dMD3TABRlcgvlL6XvyxYNJCK5V7oHF9RMNfiBWske7OuM3MiqwpBRy6S/ g==; X-IronPort-AV: E=Sophos;i="5.96,171,1665471600"; d="scan'208";a="189356168" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Nov 2022 03:53:11 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 17 Nov 2022 03:53:08 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 17 Nov 2022 03:53:06 -0700 From: Tudor Ambarus To: , , , , , CC: , , , , , Tudor Ambarus Subject: [PATCH 5/8] ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its maximum frequency Date: Thu, 17 Nov 2022 12:52:46 +0200 Message-ID: <20221117105249.115649-6-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221117105249.115649-1-tudor.ambarus@microchip.com> References: <20221117105249.115649-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221117_025314_448932_1FA701F7 X-CRM114-Status: UNSURE ( 9.92 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org sama5d27-wlsom1 populates an sst26vf064b SPI NOR flash. Its maximum operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V, increase its maximum supported frequency to 104MHz. The increasing of the spi-max-frequency value requires the setting of the "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7. The sst26vf064b datasheet specifies just a minimum value for the "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no maximum time specified. I determined experimentally that 5 ns for the spi-cs-setup-ns is not enough when the flash is operated close to its maximum frequency and tests showed that 7 ns is just fine, so set the spi-cs-setup-ns dt property to 7. With the increase of frequency the reads are now faster with ~37%. Signed-off-by: Tudor Ambarus --- arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi index 83bcf9fe0152..20caf40b4755 100644 --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi @@ -220,7 +220,8 @@ qspi1_flash: flash@0 { #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <80000000>; + spi-max-frequency = <104000000>; + spi-cs-setup-ns = /bits/ 16 <7>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; m25p,fast-read;