From patchwork Tue Nov 22 16:32:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13052561 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 98065C4332F for ; Tue, 22 Nov 2022 16:33:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=dP42p4y/DV5ZG0NnYDkxB1ikVelPmRbeIR/fPg9boZE=; b=I7LvJVwdys15TI TbrwVeKitjo1P6QEttcbwhUI0l/FL2KN0btoQtCOds4FaHO9J/mtm5Y203jFwSSyAVSdZca/j5+bs ajdwsV6vAWkvQAr+jWEgFa+FDbyDSTAmWy8hpHUFl4x4ifgyVrCmg+saTnJbdJrQh+MIiNoZR1Ybw cv0LdVOYrgeaGZWClkEv4XOjM0ilF+Bb2iQf5fev9nq8L204Q3gntOV1MyXig5BQR/TpDLU/EXm2G ZaYv4KevD46/DoHFuyqM+XNcEVdUlDvVc7jhpWAr9O6oYpfM9by4q9LDj/34i+psxReBot2wp0Crb +Ud37j+6KkJK9ltHuRSw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oxWCR-00Ak8a-Ui; Tue, 22 Nov 2022 16:32:44 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oxWCN-00Ak4p-6b; Tue, 22 Nov 2022 16:32:41 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D1AAD23A; Tue, 22 Nov 2022 08:32:40 -0800 (PST) Received: from pierre123.arm.com (pierre123.nice.arm.com [10.34.100.128]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3730B3F73D; Tue, 22 Nov 2022 08:32:32 -0800 (PST) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: Pierre Gondois , Rob Herring , Krzysztof Kozlowski , Florian Fainelli , Broadcom internal kernel review list , Ray Jui , Scott Branden , William Zhang , Anand Gore , Kursad Oney , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 1/2] arm: dts: Update cache properties for broadcom Date: Tue, 22 Nov 2022 17:32:06 +0100 Message-Id: <20221122163208.3810985-2-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221122163208.3810985-1-pierre.gondois@arm.com> References: <20221122163208.3810985-1-pierre.gondois@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221122_083239_376893_7B43F79C X-CRM114-Status: UNSURE ( 8.24 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois --- arch/arm/boot/dts/bcm2711.dtsi | 1 + arch/arm/boot/dts/bcm2836.dtsi | 1 + arch/arm/boot/dts/bcm2837.dtsi | 1 + arch/arm/boot/dts/bcm47622.dtsi | 1 + arch/arm/boot/dts/bcm63148.dtsi | 1 + arch/arm/boot/dts/bcm63178.dtsi | 1 + arch/arm/boot/dts/bcm6756.dtsi | 1 + arch/arm/boot/dts/bcm6846.dtsi | 1 + arch/arm/boot/dts/bcm6855.dtsi | 1 + arch/arm/boot/dts/bcm6878.dtsi | 1 + 10 files changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi index 941c4d16791b..c6104149f959 100644 --- a/arch/arm/boot/dts/bcm2711.dtsi +++ b/arch/arm/boot/dts/bcm2711.dtsi @@ -536,6 +536,7 @@ cpu3: cpu@3 { */ l2: l2-cache0 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set diff --git a/arch/arm/boot/dts/bcm2836.dtsi b/arch/arm/boot/dts/bcm2836.dtsi index 534dacfc4dd5..547ecc210f18 100644 --- a/arch/arm/boot/dts/bcm2836.dtsi +++ b/arch/arm/boot/dts/bcm2836.dtsi @@ -113,6 +113,7 @@ v7_cpu3: cpu@3 { */ l2: l2-cache0 { compatible = "cache"; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi index 5dbdebc46259..b352ac784af6 100644 --- a/arch/arm/boot/dts/bcm2837.dtsi +++ b/arch/arm/boot/dts/bcm2837.dtsi @@ -115,6 +115,7 @@ cpu3: cpu@3 { */ l2: l2-cache0 { compatible = "cache"; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set diff --git a/arch/arm/boot/dts/bcm47622.dtsi b/arch/arm/boot/dts/bcm47622.dtsi index 2df04528af82..f4b2db9bc4ab 100644 --- a/arch/arm/boot/dts/bcm47622.dtsi +++ b/arch/arm/boot/dts/bcm47622.dtsi @@ -51,6 +51,7 @@ CA7_3: cpu@3 { L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm/boot/dts/bcm63148.dtsi b/arch/arm/boot/dts/bcm63148.dtsi index df5307b6b3af..7cd55d64de71 100644 --- a/arch/arm/boot/dts/bcm63148.dtsi +++ b/arch/arm/boot/dts/bcm63148.dtsi @@ -35,6 +35,7 @@ B15_1: cpu@1 { L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm/boot/dts/bcm63178.dtsi b/arch/arm/boot/dts/bcm63178.dtsi index cbd094dde6d0..043e699cbc27 100644 --- a/arch/arm/boot/dts/bcm63178.dtsi +++ b/arch/arm/boot/dts/bcm63178.dtsi @@ -43,6 +43,7 @@ CA7_2: cpu@2 { L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm/boot/dts/bcm6756.dtsi b/arch/arm/boot/dts/bcm6756.dtsi index ce1b59faf800..5c72219bc194 100644 --- a/arch/arm/boot/dts/bcm6756.dtsi +++ b/arch/arm/boot/dts/bcm6756.dtsi @@ -51,6 +51,7 @@ CA7_3: cpu@3 { L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm/boot/dts/bcm6846.dtsi b/arch/arm/boot/dts/bcm6846.dtsi index 8aa47a2583b2..81513a793815 100644 --- a/arch/arm/boot/dts/bcm6846.dtsi +++ b/arch/arm/boot/dts/bcm6846.dtsi @@ -35,6 +35,7 @@ CA7_1: cpu@1 { L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm/boot/dts/bcm6855.dtsi b/arch/arm/boot/dts/bcm6855.dtsi index 620f51aee1a2..5fa5feac0e29 100644 --- a/arch/arm/boot/dts/bcm6855.dtsi +++ b/arch/arm/boot/dts/bcm6855.dtsi @@ -43,6 +43,7 @@ CA7_2: cpu@2 { L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm/boot/dts/bcm6878.dtsi b/arch/arm/boot/dts/bcm6878.dtsi index 1e8b5fa96c25..4ec836ac4baf 100644 --- a/arch/arm/boot/dts/bcm6878.dtsi +++ b/arch/arm/boot/dts/bcm6878.dtsi @@ -35,6 +35,7 @@ CA7_1: cpu@1 { L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; };