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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jT9o6Icc5JjNxVYmz9Wu0qTWQxpiTKb4onx2/brrnWbMh74wWw7MTeOvCyohT2bFlQgngx5uHZi3YcRDifCe//WpMLniKC9aV4fWR4jrMU5tqnStN+Qv7HgKXEdAbj7MpzCsqI5Bw9ywdFsSFWQ16QmkXB68smyYflX6i9O73SfuuVOVshy+6hC4ADErwem0+Z+Q+HiU0OPCtPhOFkz477e14NcEjVKWQSyDn4vpESHMYH1WiZSlB9NgSSyy1+P3OBWBoOUQUhPHN8KpDN/F4k2jFZNRaAbSEQPt8qKfORsTcBC+K0QqncQ8rSBhap381pJNdOrbpZDFbHH5nH8JVMliiA/B2htm6MuwkN+Hu7VSmYnpNBGq+D4SFGkMetPeBOBf16MtcDj2+Qaa0VEAclXJVOL5jV4JoVUjqBvTabRzAdmt8KHHJGHsw/9jdNxnjHUVNbOeSeSORjz6RXyrf7opw//gLhjqPFBGQaR/K3jubShQnXjKqltbguyZEbK0bRCp2IZqkch+2XOm3oFFa79ofVfYiYQNbDCp7qV3oxsgf1X/IA7USdurUINrMAprp5l2tYfDlexRsFo9ApN+SEVye9qfXbiEhpuy/w3FeUfL3WAtbjR4fiPGpIJnd4/Tg2UMtZ6Nmth2W4hP0wCuzC8FZSR/wzu1D4mB9RYliprgVps2WKKQJphfffd2f6RjcJnRkWMI8p+k3iYeejI0zqG9PvWJIyh28+afi7K2l/oOBREQn03U1/yUcl8DzK9nXsyVsyQAcS9vrtoD65kUVFUTm9/jdBKK+68FMxeklSRSSkDTwp1PrK2mJV6dx46wXCLUlPj36zKvlGA8hi7dd8pKYEAoiry0sA+QOB4+r2Gt1xigHzsqkjHBjQD2angHWWBl4Q17wu3uSNegKvoilI+3SuhYkCb/ffMe4Dov8VQk8OG0RahlN3ZjwXXoO18u9ZO7XFHk95FH4CcrLPg0DyThEqUyS2dTaNlwYOFKDWNiK8mzb10LQALQaOI2PnNfgFxXgNWqIfTnlC7JKlNHR8qWZwhxrPodBXniKACRWVw7jyW7kS5W7JOHinMmrQY9b1BUPEVr8YKcQBVp0R3S0i9BCvFiw+Um66C+E5rL+rrsEpO+k81ffxRrEXGYsVY5K3+6Ufuqry1PgyFQwGu8XI7y4FC3q5oGaREwmnXwOqDP5w9j7ptp3Eo238prnZv3gOKAyBg8rg2PPasiLxZUE5ETmsHnsQEoRUa3UxtgtKSMmh0qkTRR8jApd9wwv+8ExJhTiiz/zmioyPPM2MC8PgSlSS3zAF/B9gHynDTR0lGPOs036J4GCw/jlCyYS9x0XbOZFhyMCterUu4bxUo/gAa2WprFhsh37vi5Nl4a+eMtL/9vrFMkGRfvbTSTdWCetHz8dRgHgOof5uR5l//kA42/f3e/DA+JlFCSEqxKDK+y0X1tLFbVwMEZrEjiZt4vDyi29og1W7ToQh4+JcHOsRWV68cw4onwop2hIBnU3u0xGc8maYTsP8FQfYOIpe5iy00vat24C0ku/7pehGFifQb1hoJWXMnHlRgpCI3lxSBRhq19ytWDycQvnb9XMYzfZU2IEXGHbcuPZLwyCbDvGw== X-OriginatorOrg: plvision.eu X-MS-Exchange-CrossTenant-Network-Message-Id: 779bcf49-8303-42fe-c21b-08dace24070d X-MS-Exchange-CrossTenant-AuthSource: VI1P190MB0317.EURP190.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Nov 2022 13:58:56.6488 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 03707b74-30f3-46b6-a0e0-ff0a7438c9c4 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: xKOD06exHN/wcvrRXOotE+/jRWNYF7LzYZtcYDrWoSfvz6iTaO5JT3wNQtu+Tbm82/YBAnV7sXxRW/eVII1Cxj+C2cfXrnBdUoRcjQ9tfGs= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM7P190MB0758 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221124_055904_181583_E61AA33E X-CRM114-Status: GOOD ( 15.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yuval Shaia AC5 requires different handling for MSI as with armada8k. Fix it by: 1. Enabling the relevant bits in init phase 2. Dispatch virtual IRQ handlers when MSI interrupts are received Also enable/disable PCIE_APP_LTSSM for AC5. Signed-off-by: Yuval Shaia Signed-off-by: Vadym Kochan --- v2: 1) fix W1 warnings which caused by unused leftover code 2) fix type in "requieres" word in the description drivers/pci/controller/dwc/pcie-armada8k.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c index bbe9a1750d0d..7e02eddaeac0 100644 --- a/drivers/pci/controller/dwc/pcie-armada8k.c +++ b/drivers/pci/controller/dwc/pcie-armada8k.c @@ -50,6 +50,7 @@ struct armada8k_pcie_of_data { #define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0) #define PCIE_APP_LTSSM_EN BIT(2) +#define PCIE_APP_LTSSM_EN_AC5 BIT(24) #define PCIE_DEVICE_TYPE_SHIFT 4 #define PCIE_DEVICE_TYPE_MASK 0xF #define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */ @@ -69,6 +70,7 @@ struct armada8k_pcie_of_data { #define PCIE_INT_B_ASSERT_MASK_AC5 BIT(13) #define PCIE_INT_C_ASSERT_MASK_AC5 BIT(14) #define PCIE_INT_D_ASSERT_MASK_AC5 BIT(15) +#define PCIE_MSI_MASK_AC5 BIT(11) #define PCIE_ATU_ACCESS_MASK_AC5 GENMASK(21, 20) @@ -172,6 +174,16 @@ static int armada8k_pcie_link_up(struct dw_pcie *pci) return 0; } +static void ac5_pcie_msi_init(struct dw_pcie *pci) +{ + u32 val; + + /* Set MSI bit in interrupt mask */ + val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG); + val |= PCIE_MSI_MASK_AC5; + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, val); +} + static int armada8k_pcie_host_init(struct dw_pcie_rp *pp) { u32 reg; @@ -181,7 +193,10 @@ static int armada8k_pcie_host_init(struct dw_pcie_rp *pp) if (!dw_pcie_link_up(pci)) { /* Disable LTSSM state machine to enable configuration */ reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); - reg &= ~(PCIE_APP_LTSSM_EN); + if (pcie->pcie_type == ARMADA8K_PCIE_TYPE_AC5) + reg &= ~(PCIE_APP_LTSSM_EN_AC5); + else + reg &= ~(PCIE_APP_LTSSM_EN); dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); } @@ -221,6 +236,9 @@ static int armada8k_pcie_host_init(struct dw_pcie_rp *pp) dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg); } + if (IS_ENABLED(CONFIG_PCI_MSI) && (pcie->pcie_type == ARMADA8K_PCIE_TYPE_AC5)) + ac5_pcie_msi_init(pci); + return 0; } @@ -237,6 +255,8 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) */ val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG); dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val); + if ((PCIE_MSI_MASK_AC5 & val) && (pcie->pcie_type == ARMADA8K_PCIE_TYPE_AC5)) + dw_handle_msi_irq(&pci->pp); return IRQ_HANDLED; }