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[46.135.44.69]) by smtp.gmail.com with ESMTPSA id g1-20020a17090604c100b007c07b23a79bsm1592400eja.213.2022.12.01.02.30.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 02:30:57 -0800 (PST) From: Tomeu Vizoso To: Cc: italonicola@collabora.com, Tomeu Vizoso , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Amlogic Meson SoC support), linux-amlogic@lists.infradead.org (open list:ARM/Amlogic Meson SoC support), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 2/7] dt-bindings: power: Add G12A NNA power domain Date: Thu, 1 Dec 2022 11:30:18 +0100 Message-Id: <20221201103026.53234-3-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221201103026.53234-1-tomeu.vizoso@collabora.com> References: <20221201103026.53234-1-tomeu.vizoso@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221201_023100_729137_441389F9 X-CRM114-Status: UNSURE ( 8.10 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add define for the NNA power domain for the NPU in the G12A. Signed-off-by: Tomeu Vizoso Acked-by: Neil Armstrong Reviewed-by: Martin Blumenstingl --- include/dt-bindings/power/meson-g12a-power.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/power/meson-g12a-power.h b/include/dt-bindings/power/meson-g12a-power.h index bb5e67a842de..93b03bdd60b7 100644 --- a/include/dt-bindings/power/meson-g12a-power.h +++ b/include/dt-bindings/power/meson-g12a-power.h @@ -9,5 +9,6 @@ #define PWRC_G12A_VPU_ID 0 #define PWRC_G12A_ETH_ID 1 +#define PWRC_G12A_NNA_ID 2 #endif