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Thu, 01 Dec 2022 02:49:57 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id 4-20020a630804000000b004785a63b44bsm2320580pgi.43.2022.12.01.02.49.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 02:49:57 -0800 (PST) From: Akihiko Odaki To: Cc: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Marc Zyngier , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH 3/3] KVM: arm64: Handle CCSIDR associativity mismatches Date: Thu, 1 Dec 2022 19:49:14 +0900 Message-Id: <20221201104914.28944-4-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221201104914.28944-1-akihiko.odaki@daynix.com> References: <20221201104914.28944-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221201_025013_718337_4D40820D X-CRM114-Status: GOOD ( 14.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org CCSIDR associativity mismatches among the physical CPUs causes a vCPU see inconsistent values when it is migrated among physical CPUs. It also makes QEMU fail restoring the vCPU registers because QEMU saves and restores all of the registers including CCSIDRs, and if the vCPU migrated among physical CPUs between saving and restoring, it tries to restore CCSIDR values that mismatch with the current physical CPU, which causes EFAULT. Trap CCSIDRs if there are CCSIDR value msimatches, and override the associativity bits when handling the trap. Signed-off-by: Akihiko Odaki --- arch/arm64/include/asm/kvm_emulate.h | 1 + arch/arm64/kvm/sys_regs.c | 7 ++++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h index b45cf8903190..df2bab867e12 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -64,6 +64,7 @@ static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu) static inline bool vcpu_cache_overridden(struct kvm_vcpu *vcpu) { return cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE) || + cpus_have_const_cap(ARM64_MISMATCHED_CACHE_ASSOCIATIVITY) || vcpu_el1_is_32bit(vcpu); } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 1f0cb015e81c..181a5b215a0e 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -110,8 +110,13 @@ static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) * [If guests should attempt to infer aliasing properties from the * geometry (which is not permitted by the architecture), they would * only do so for virtually indexed caches.] + * + * This also makes sure the associativity bits of the CCSIDRs, including + * the ones of CCSIDRs for instruction caches, are overridden when the + * physical CPUs have a heterogeneous configuration so that a vCPU sees + * the consistent values if it is migrated among physical CPUs. */ - if (vcpu_cache_overridden(vcpu) && !(csselr & CSSELR_IN)) // data or unified cache + if (vcpu_cache_overridden(vcpu)) ccsidr &= ~CCSIDR_ASSOCIATIVITY_BITS_MASK; return ccsidr;