From patchwork Mon Dec 5 06:57:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiangsheng Hou X-Patchwork-Id: 13064233 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3948EC4321E for ; Mon, 5 Dec 2022 07:49:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=E00gAgLY4eb9zVG1OVCy/V64mWqQIPYf/aF5mCeYMas=; b=UZt6ZxoO6nCe1k +R6b8mP6fHLE0HjcbfWr0k2ZLIBo4orHTyE95R3+Z8rG5cMCXCxDp/Z94umbJaZlD1Pcpy7uLayQK prXaXCo/ITnbHpGTLzSmIHbk/3ZuwUYfOML0xnGYEaTI33wNBcE+TfPfg0GNmJKquItbUcF++dK3c pD85PW86QHsyf3kngJxFKgW8DoR25kjFKDCU3JOpUCGOIegbzh4EpDp7bH6zL4gYAed3KHK2KTR9K LmPR60/KA+yMl6OyiQCDFTR19Levx5vrC994+CthHpp/4nSVs/202Weqf+cSIYx90htUNFBttVoeY 03+K78nKjURQGC3Qh4PQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p26Dh-00FqIU-8x; Mon, 05 Dec 2022 07:48:57 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p26Dc-00FqGy-J4; Mon, 05 Dec 2022 07:48:54 +0000 X-UUID: 85cc204b41ab45378d28218139a48226-20221205 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=1WMPHgGT2Vc06cNDWGV7eQXxRmPqVm37oCGD2yTJxvQ=; b=DOLBopSdwrxYRACR642xEdclstPqvpiA15BQILD3PwlcKb9dYkhO9ZHgwReZgPTj2hG5d2I1MM+cmcg9/YvWSSMIlCY7IM3JaswwpivhfEDHtEniCOitZogRYfClAFMRbcmQX52eus4zpeskonYOegjmiHzzEmoEUBq+AvXYudQ=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:e27d2e44-f329-49cc-ab86-26ed1d16fc0c,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:dcaaed0,CLOUDID:4e21b030-2938-482e-aafd-98d66723b8a9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 85cc204b41ab45378d28218139a48226-20221205 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 175316104; Mon, 05 Dec 2022 00:48:48 -0700 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 5 Dec 2022 14:58:09 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 5 Dec 2022 14:58:08 +0800 From: Xiangsheng Hou To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Mark Brown , Chuanhong Guo CC: Xiangsheng Hou , , , , , , , , Subject: [PATCH v2 1/9] spi: mtk-snfi: Add snfi support for MT7986 IC Date: Mon, 5 Dec 2022 14:57:48 +0800 Message-ID: <20221205065756.26875-2-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221205065756.26875-1-xiangsheng.hou@mediatek.com> References: <20221205065756.26875-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221204_234852_658581_E0ED9E01 X-CRM114-Status: GOOD ( 13.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add snfi support for MT7986 IC. Signed-off-by: Xiangsheng Hou Reviewed-by: AngeloGioacchino Del Regno --- drivers/spi/spi-mtk-snfi.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-mtk-snfi.c b/drivers/spi/spi-mtk-snfi.c index d66bf9762557..fa8412ba20e2 100644 --- a/drivers/spi/spi-mtk-snfi.c +++ b/drivers/spi/spi-mtk-snfi.c @@ -126,7 +126,8 @@ #define STR_DATA BIT(0) #define NFI_STA 0x060 -#define NFI_NAND_FSM GENMASK(28, 24) +#define NFI_NAND_FSM_7622 GENMASK(28, 24) +#define NFI_NAND_FSM_7986 GENMASK(29, 23) #define NFI_FSM GENMASK(19, 16) #define READ_EMPTY BIT(12) @@ -158,6 +159,7 @@ #define MAS_WR GENMASK(5, 3) #define MAS_RDDLY GENMASK(2, 0) #define NFI_MASTERSTA_MASK_7622 (MAS_ADDR | MAS_RD | MAS_WR | MAS_RDDLY) +#define NFI_MASTERSTA_MASK_7986 3 // SNFI registers #define SNF_MAC_CTL 0x500 @@ -220,6 +222,11 @@ static const u8 mt7622_spare_sizes[] = { 16, 26, 27, 28 }; +static const u8 mt7986_spare_sizes[] = { + 16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 61, 63, 64, 67, + 74 +}; + struct mtk_snand_caps { u16 sector_size; u16 max_sectors; @@ -230,6 +237,7 @@ struct mtk_snand_caps { bool bbm_swap; bool empty_page_check; u32 mastersta_mask; + u32 nandfsm_mask; const u8 *spare_sizes; u32 num_spare_size; @@ -244,6 +252,7 @@ static const struct mtk_snand_caps mt7622_snand_caps = { .bbm_swap = false, .empty_page_check = false, .mastersta_mask = NFI_MASTERSTA_MASK_7622, + .nandfsm_mask = NFI_NAND_FSM_7622, .spare_sizes = mt7622_spare_sizes, .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes) }; @@ -257,10 +266,25 @@ static const struct mtk_snand_caps mt7629_snand_caps = { .bbm_swap = true, .empty_page_check = false, .mastersta_mask = NFI_MASTERSTA_MASK_7622, + .nandfsm_mask = NFI_NAND_FSM_7622, .spare_sizes = mt7622_spare_sizes, .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes) }; +static const struct mtk_snand_caps mt7986_snand_caps = { + .sector_size = 1024, + .max_sectors = 8, + .fdm_size = 8, + .fdm_ecc_size = 1, + .fifo_size = 64, + .bbm_swap = true, + .empty_page_check = true, + .mastersta_mask = NFI_MASTERSTA_MASK_7986, + .nandfsm_mask = NFI_NAND_FSM_7986, + .spare_sizes = mt7986_spare_sizes, + .num_spare_size = ARRAY_SIZE(mt7986_spare_sizes) +}; + struct mtk_snand_conf { size_t page_size; size_t oob_size; @@ -360,7 +384,7 @@ static int mtk_nfi_reset(struct mtk_snand *snf) } ret = readl_poll_timeout(snf->nfi_base + NFI_STA, val, - !(val & (NFI_FSM | NFI_NAND_FSM)), 0, + !(val & (NFI_FSM | snf->caps->nandfsm_mask)), 0, SNFI_POLL_INTERVAL); if (ret) { dev_err(snf->dev, "Failed to reset NFI\n"); @@ -1295,6 +1319,7 @@ static irqreturn_t mtk_snand_irq(int irq, void *id) static const struct of_device_id mtk_snand_ids[] = { { .compatible = "mediatek,mt7622-snand", .data = &mt7622_snand_caps }, { .compatible = "mediatek,mt7629-snand", .data = &mt7629_snand_caps }, + { .compatible = "mediatek,mt7986-snand", .data = &mt7986_snand_caps }, {}, };