| Message ID | 20221206135930.3277585-2-ryan.roberts@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM: arm64: Support FEAT_LPA2 at hyp s1 and vm s2 | expand |
On Tue, Dec 06, 2022 at 01:59:19PM +0000, Ryan Roberts wrote: > From: Anshuman Khandual <anshuman.khandual@arm.com> > > PAGE_SIZE support is tested against possible minimum and maximum values for > its respective ID_AA64MMFR0.TGRAN field, depending on whether it is signed > or unsigned. But then FEAT_LPA2 implementation needs to be validated for 4K > and 16K page sizes via feature specific ID_AA64MMFR0.TGRAN values. Hence it > adds FEAT_LPA2 specific ID_AA64MMFR0.TGRAN[2] values per ARM ARM (0487G.A). > > Acked-by: Catalin Marinas <catalin.marinas@arm.com> > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> > Signed-off-by: Ryan Roberts <ryan.roberts@arm.com> > --- > arch/arm64/include/asm/sysreg.h | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 7d301700d1a9..9ad8172eea58 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -673,10 +673,12 @@ > > /* id_aa64mmfr0 */ > #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 0x0 > +#define ID_AA64MMFR0_EL1_TGRAN4_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT > #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 0x7 > #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 0x0 > #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 0x7 > #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 0x1 > +#define ID_AA64MMFR0_EL1_TGRAN16_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT > #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 0xf > > #define ARM64_MIN_PARANGE_BITS 32 > @@ -684,6 +686,7 @@ > #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT 0x0 > #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE 0x1 > #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN 0x2 > +#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2 0x3 > #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7 > > #ifdef CONFIG_ARM64_PA_BITS_52 > @@ -800,11 +803,13 @@ > > #if defined(CONFIG_ARM64_4K_PAGES) > #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT > +#define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT > #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN > #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX > #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT > #elif defined(CONFIG_ARM64_16K_PAGES) > #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN16_SHIFT > +#define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT Can you use the 52_BIT suffix instead for these macros? LPA2 can map to multiple values (i.e. no support for 4KB granule). Also provides a direct description of what feature we're testing for. -- Thanks, Oliver
On Wed, Dec 14, 2022 at 07:16:09PM +0000, Oliver Upton wrote: > On Tue, Dec 06, 2022 at 01:59:19PM +0000, Ryan Roberts wrote: > > From: Anshuman Khandual <anshuman.khandual@arm.com> > > > > PAGE_SIZE support is tested against possible minimum and maximum values for > > its respective ID_AA64MMFR0.TGRAN field, depending on whether it is signed > > or unsigned. But then FEAT_LPA2 implementation needs to be validated for 4K > > and 16K page sizes via feature specific ID_AA64MMFR0.TGRAN values. Hence it > > adds FEAT_LPA2 specific ID_AA64MMFR0.TGRAN[2] values per ARM ARM (0487G.A). > > > > Acked-by: Catalin Marinas <catalin.marinas@arm.com> > > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> > > Signed-off-by: Ryan Roberts <ryan.roberts@arm.com> > > --- > > arch/arm64/include/asm/sysreg.h | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > > index 7d301700d1a9..9ad8172eea58 100644 > > --- a/arch/arm64/include/asm/sysreg.h > > +++ b/arch/arm64/include/asm/sysreg.h > > @@ -673,10 +673,12 @@ > > > > /* id_aa64mmfr0 */ > > #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 0x0 > > +#define ID_AA64MMFR0_EL1_TGRAN4_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT > > #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 0x7 > > #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 0x0 > > #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 0x7 > > #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 0x1 > > +#define ID_AA64MMFR0_EL1_TGRAN16_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT > > #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 0xf > > > > #define ARM64_MIN_PARANGE_BITS 32 > > @@ -684,6 +686,7 @@ > > #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT 0x0 > > #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE 0x1 > > #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN 0x2 > > +#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2 0x3 > > #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7 > > > > #ifdef CONFIG_ARM64_PA_BITS_52 > > @@ -800,11 +803,13 @@ > > > > #if defined(CONFIG_ARM64_4K_PAGES) > > #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT > > +#define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT > > #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN > > #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX > > #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT > > #elif defined(CONFIG_ARM64_16K_PAGES) > > #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN16_SHIFT > > +#define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT > > Can you use the 52_BIT suffix instead for these macros? LPA2 can map to > multiple values (i.e. no support for 4KB granule). Also provides a > direct description of what feature we're testing for. Ignore me. I had to educate myself with Ard's series, and I now see that this pattern is followed there too. -- Thanks, Oliver
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 7d301700d1a9..9ad8172eea58 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -673,10 +673,12 @@ /* id_aa64mmfr0 */ #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 0x0 +#define ID_AA64MMFR0_EL1_TGRAN4_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 0x7 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 0x0 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 0x7 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 0x1 +#define ID_AA64MMFR0_EL1_TGRAN16_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 0xf #define ARM64_MIN_PARANGE_BITS 32 @@ -684,6 +686,7 @@ #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT 0x0 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE 0x1 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN 0x2 +#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2 0x3 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7 #ifdef CONFIG_ARM64_PA_BITS_52 @@ -800,11 +803,13 @@ #if defined(CONFIG_ARM64_4K_PAGES) #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT +#define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT #elif defined(CONFIG_ARM64_16K_PAGES) #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN16_SHIFT +#define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT