From patchwork Tue Dec 6 13:59:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Roberts X-Patchwork-Id: 13065846 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C5215C352A1 for ; Tue, 6 Dec 2022 14:02:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=7yG+jEeD3JjTCNcSrQTqWi9jT08+SN46kfN6YdPCdn4=; b=vwY8VkzMV9cqSc HJZJ62TaeLJJ3GitTRepsblIPRSBjfoamY9fPhcAbqOnqlZepbycvNpiP9/1d78bNwL4Cpo9aLhUC SYRXsjU0cPD2g+tzsovGyZA7OU5jGiL3XzqKtDzS+jMb6Td8wXAzLBiOqDIT61/lHQvzsVkvocEDl Lq15fXKt74qpVaAfA3n+vJRlS97lqocQJywoa9LJPCNEElO5DLTjeESK144Bc/dxwJ/sX84cZu6LL 2uiGyYhBB1FOtibMy6PkIcM9mhs0kMIXMIASzcbIHkCjfC3sd/zZEJIr7tZbr3mCkK3pIJRnsTZVf OZnxsphFcf3kS6Jk0BYw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p2YUn-00A9Mb-Ks; Tue, 06 Dec 2022 14:00:29 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p2YUW-00A959-7X for linux-arm-kernel@lists.infradead.org; Tue, 06 Dec 2022 14:00:15 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E279412FC; Tue, 6 Dec 2022 06:00:14 -0800 (PST) Received: from e125769.cambridge.arm.com (e125769.cambridge.arm.com [10.1.196.159]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 87D623F73D; Tue, 6 Dec 2022 06:00:06 -0800 (PST) From: Ryan Roberts To: Marc Zyngier , Catalin Marinas , Will Deacon , Ard Biesheuvel , Suzuki K Poulose , Anshuman Khandual Cc: Ryan Roberts , James Morse , Alexandru Elisei , Oliver Upton , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu Subject: [PATCH v1 03/12] KVM: arm64: Add new (V)TCR_EL2 field definitions for FEAT_LPA2 Date: Tue, 6 Dec 2022 13:59:21 +0000 Message-Id: <20221206135930.3277585-4-ryan.roberts@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221206135930.3277585-1-ryan.roberts@arm.com> References: <20221206135930.3277585-1-ryan.roberts@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221206_060012_347315_143CAC82 X-CRM114-Status: UNSURE ( 7.89 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org As per Arm ARM (0487I.a), (V)TCR_EL2.DS fields control whether 52 bit input and output addresses are supported on 4K and 16K page size configurations when FEAT_LPA2 is known to have been implemented. Additionally, VTCR_EL2.SL2 field is added to enable encoding of a 5th starting level of translation, which is required with 4KB IPA size of 49-52 bits if concatenated first level page tables are not used. This adds these field definitions which will be used by KVM when FEAT_LPA2 is enabled. Signed-off-by: Ryan Roberts --- arch/arm64/include/asm/kvm_arm.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index a82f2493a72b..f9619a10d5d9 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -92,6 +92,7 @@ #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H) /* TCR_EL2 Registers bits */ +#define TCR_EL2_DS (1UL << 32) #define TCR_EL2_RES1 ((1U << 31) | (1 << 23)) #define TCR_EL2_TBI (1 << 20) #define TCR_EL2_PS_SHIFT 16 @@ -106,6 +107,9 @@ TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK) /* VTCR_EL2 Registers bits */ +#define VTCR_EL2_SL2_SHIFT 33 +#define VTCR_EL2_SL2_MASK (1UL << VTCR_EL2_SL2_SHIFT) +#define VTCR_EL2_DS TCR_EL2_DS #define VTCR_EL2_RES1 (1U << 31) #define VTCR_EL2_HD (1 << 22) #define VTCR_EL2_HA (1 << 21)