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[82.54.95.136]) by smtp.gmail.com with ESMTPSA id k10-20020a056000004a00b002365730eae8sm17298534wrx.55.2022.12.06.09.11.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 09:11:08 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Amarula patchwork , Dario Binacchi , Arnd Bergmann , Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team , Russell King , Sascha Hauer , Shawn Guo , linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/5] ARM: imx27: add missing of_node_put() Date: Tue, 6 Dec 2022 18:10:46 +0100 Message-Id: <20221206171049.3316611-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221206171049.3316611-1-dario.binacchi@amarulasolutions.com> References: <20221206171049.3316611-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221206_091110_634870_40204CB3 X-CRM114-Status: UNSURE ( 9.76 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In mx27_read_cpu_rev(), of_find_compatible_node() returns a node pointer with refcount incremented. Use of_node_put() on it when done. Fixes: 94b2bec1b0e05 ("ARM: imx27: Retrieve the SYSCTRL base address from devicetree") Signed-off-by: Dario Binacchi --- arch/arm/mach-imx/cpu-imx27.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/cpu-imx27.c b/arch/arm/mach-imx/cpu-imx27.c index bf70e13bbe9e..1d2893908368 100644 --- a/arch/arm/mach-imx/cpu-imx27.c +++ b/arch/arm/mach-imx/cpu-imx27.c @@ -28,6 +28,7 @@ static int mx27_read_cpu_rev(void) np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm"); ccm_base = of_iomap(np, 0); + of_node_put(np); BUG_ON(!ccm_base); /* * now we have access to the IO registers. As we need