From patchwork Mon Dec 19 08:43:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carlo Caione X-Patchwork-Id: 13076359 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 55B87C10F1B for ; Mon, 19 Dec 2022 08:44:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Message-Id:MIME-Version:Subject: Date:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=LQcTPiK5ppsfrQbvFu5VpGYDEryPSwT4m2//Wmtg0tw=; b=ho67XGGdiIzTrX S4eMPWkEAB0co4o+UmcVNPiGQ6aAtfwThAOdOo6EjUrzzDN+3OLcs3B2KyczDGvm2EFa0w64M4ioB 70K2vC0qrNYZDrf760vdB7i8mFaCSC9UDhDkc3NglcdHbcqLIezMGxAS89ma10YU3rILRdgUeipA8 bTmI/quj6NmRrxouFJiPwzF/iiqzN89KZqoAuo6SEEy8uz4GdFlhxeKl4VIlxypPLTmFMEwS9T0le aMEc6IuroNXSUolOVElFGSQN/pEGeBD6AVPL/vesVxb2zIu6RgctFRLoLBSXaC/hevCh/yxHzOQDt sJ0mqS4EV3+gXTVPM3Ug==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p7Bk9-00AjZk-FA; Mon, 19 Dec 2022 08:43:29 +0000 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p7Bk3-00AjTr-Ha for linux-arm-kernel@lists.infradead.org; Mon, 19 Dec 2022 08:43:27 +0000 Received: by mail-ej1-x62f.google.com with SMTP id kw15so19683910ejc.10 for ; Mon, 19 Dec 2022 00:43:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:message-id:content-transfer-encoding:mime-version:subject :date:from:from:to:cc:subject:date:message-id:reply-to; bh=kYYaE3bwqOZpjy9bqglp5kw8THeTMFyYTG3Pe3WusMY=; b=73G2LxFwIuXcJ8JfikxHBeTK8Ai8+099d7TsNEgBayS3aGnT3o3UhXd2w5UnDtt3Ia 0sIi4pHg+1OyBNaU//uOizs1AYrUWG3CyYuYFuOI1PE5M5UPmWEfmAZhzFVLQro/CjuR nOevReLfQUP7X4vhPqEh1sfp38tL+m0m27GS4zbsfo5WkN1gzXKerBonhxbzgq4fiC+l 5XQY4rvgo80IFX4GjhiUWF8UjdWrPH9ncuS0egroDJR7bwpeaLjA3a3sZe7nxggczXLQ dDh9f93/9dRvQWVcZAD7UwR/uJEhOqRZ0xeNv/HJN2ab/rZYMMolHOLoTxlxZqJKdebN v7yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:message-id:content-transfer-encoding:mime-version:subject :date:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=kYYaE3bwqOZpjy9bqglp5kw8THeTMFyYTG3Pe3WusMY=; b=xT/6AdgmLZwzOmUKLeQDt9z4L88tesph3NnP+TNTIK40pq6Lh+EQdo3WcmpAdz00DO /feT4iG6EtG2SXFRQSBveEE4iC4MxHYoeW8/7A4un++9JYYL0uznpZsto8PgE3pJgiN5 +ZZo4MrSeZm00Cm4RTLlTh4xpIAWIBrBMczmf+8A2aH1glpZ00Y9iavyw9j9REOc0QHz TdZ4zaxoLMLu2AOlHOu7LPx/GwpPiDvrsbfKJFPK4o/ERWLrzOa5FWdKGX9wo7WCXYJ3 96C2i80ZsaLZQd0LP9KUqllzQwXzHQAlEqovaEs5sxTDNYdBXG530yZ88Ff2VmINOYvl nfSw== X-Gm-Message-State: ANoB5pmMG5/Uu2uD3vjbADxQc/hJWmmYXe4BK1Qc7qnS2Vqmgu+iK+9P dfNENHOGLc9cJ1WbVTtHwhzPKw== X-Google-Smtp-Source: AA0mqf7famYNciIPKzFQ0QR5iYvihCH5RaB2lTsclMVvpvXA8pM9J4X8rlevPiqjboKSR8SeNzSmuw== X-Received: by 2002:a17:906:8d08:b0:7c1:700:1e2d with SMTP id rv8-20020a1709068d0800b007c107001e2dmr55156347ejc.20.1671439397658; Mon, 19 Dec 2022 00:43:17 -0800 (PST) Received: from [127.0.1.1] ([2001:b07:5d39:f336:a0ba:cfa5:2107:c2c4]) by smtp.gmail.com with ESMTPSA id w7-20020a170906b18700b007c0b28b85c5sm4083755ejy.138.2022.12.19.00.43.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 00:43:17 -0800 (PST) From: Carlo Caione Date: Mon, 19 Dec 2022 09:43:05 +0100 Subject: [PATCH] drm/meson: Reduce the FIFO lines held when AFBC is not used MIME-Version: 1.0 Message-Id: <20221216-afbc_s905x-v1-0-033bebf780d9@baylibre.com> To: David Airlie , Martin Blumenstingl , Jerome Brunet , Daniel Vetter , Kevin Hilman , Neil Armstrong Cc: linux-amlogic@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Carlo Caione X-Mailer: b4 0.10.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221219_004324_051334_60C18A5A X-CRM114-Status: GOOD ( 16.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Having a bigger number of FIFO lines held after vsync is only useful to SoCs using AFBC to give time to the AFBC decoder to be reset, configured and enabled again. For SoCs not using AFBC this, on the contrary, is causing on some displays issues and a few pixels vertical offset in the displayed image. Conditionally increase the number of lines held after vsync only for SoCs using AFBC, leaving the default value for all the others. Signed-off-by: Carlo Caione Acked-by: Martin Blumenstingl Acked-by: Neil Armstrong --- Fix display issues for amlogic SoCs not using AFBC In 24e0d4058eff the number of lines held after VSYNC was incremented to give time to the AFBC decoder to do its job. This is causing an issue (seen on S905x) where the image (on some panels) is dislayed with a vertical offset. With this patch we try to keep the fix only when AFBC is actually used filtering on the SoC type. To: Neil Armstrong To: David Airlie To: Daniel Vetter To: Kevin Hilman To: Jerome Brunet To: Martin Blumenstingl Cc: dri-devel@lists.freedesktop.org Cc: linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- drivers/gpu/drm/meson/meson_viu.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) --- base-commit: 84e57d292203a45c96dbcb2e6be9dd80961d981a change-id: 20221216-afbc_s905x-4baf5fdc9970 Best regards, diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c index d4b907889a21..cd399b0b7181 100644 --- a/drivers/gpu/drm/meson/meson_viu.c +++ b/drivers/gpu/drm/meson/meson_viu.c @@ -436,15 +436,14 @@ void meson_viu_init(struct meson_drm *priv) /* Initialize OSD1 fifo control register */ reg = VIU_OSD_DDR_PRIORITY_URGENT | - VIU_OSD_HOLD_FIFO_LINES(31) | VIU_OSD_FIFO_DEPTH_VAL(32) | /* fifo_depth_val: 32*8=256 */ VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */ VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) - reg |= VIU_OSD_BURST_LENGTH_32; + reg |= (VIU_OSD_BURST_LENGTH_32 | VIU_OSD_HOLD_FIFO_LINES(31)); else - reg |= VIU_OSD_BURST_LENGTH_64; + reg |= (VIU_OSD_BURST_LENGTH_64 | VIU_OSD_HOLD_FIFO_LINES(4)); writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT)); writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT));