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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org MT8195 vdosys1 has more than 32 reset bits and a different reset base than other chips. Add the number of reset bits and reset base in mmsys private data. Signed-off-by: Nancy.Lin Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Tested-by: AngeloGioacchino Del Regno Tested-by: Bo-Chen Chen --- drivers/soc/mediatek/mt8195-mmsys.h | 1 + drivers/soc/mediatek/mtk-mmsys.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h index 454944a9409c..a6652ae63431 100644 --- a/drivers/soc/mediatek/mt8195-mmsys.h +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -75,6 +75,7 @@ #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16) #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16) +#define MT8195_VDO1_SW0_RST_B 0x1d0 #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30 #define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70 #define MT8195_VDO1_HDR_TOP_CFG 0xd00 diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 02d08f85cc1c..dc36625cd2b8 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -90,6 +90,8 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { .clk_driver = "clk-mt8195-vdo1", .routes = mmsys_mt8195_vdo1_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table), + .sw0_rst_offset = MT8195_VDO1_SW0_RST_B, + .num_resets = 64, }; static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {