From patchwork Sat Dec 31 10:47:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13086021 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ECF19C3DA7D for ; Sat, 31 Dec 2022 10:53:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6cBbGxNEsm8iZGnJJbWdbK7HDJ5MGQy5dmmYstuaq1A=; b=y2/y6mul7KmYBi kn6mwGcX4bJZofqGxeVVXCHX9vBMJbeAkd90Akty1yCJD72eC+eWkYs2NIeMVCWRHkuIqCqfSJwSG stPZy68shGvntwsghaK3OJpbtkMNN2WoDFpst3JLasE6Ool8mNCH8CIJioI7CGL+k6Um+hEZuBqZ2 kgQNGjnJ7djd2ZKYpxhyfQbvlEyLuxKcexOfyvDwjp+uo3EC+mCqg5wAEAkYVspO7DxlXPAjkBmVn sl5U10/WhUwvt10ObqA9Q7L6URSVHhrnZYdaD0Coy+U030/JKbDSJsT80GIRkScr/d66ZKKHuHCkS yNVySmzTxJBWriN9fKxg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBZTE-0045Ld-AW; Sat, 31 Dec 2022 10:52:09 +0000 Received: from mail-ed1-x533.google.com ([2a00:1450:4864:20::533]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBZPG-0042ZO-Rp for linux-arm-kernel@lists.infradead.org; Sat, 31 Dec 2022 10:48:04 +0000 Received: by mail-ed1-x533.google.com with SMTP id m21so33549673edc.3 for ; Sat, 31 Dec 2022 02:48:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lNTG6siRVvvtXsy+GAwDHHb+RGsPbfwrQN+hKdCck/s=; b=h6suuaQS77Q7uXcGE0tPIOZR6gBZPftHQtxsZiWvYKzvoFpBLYY0mo7cbC6csHNPoF 3NaUYsD6S+p2Q+FZCE0OaBn+CWnPrJ7vDGapfHiNJKYuCUAnvARnT+N8olSAMNF1QW7K O20zyLdNpY08v8qurYDkKtekosozQzLZuBqX0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lNTG6siRVvvtXsy+GAwDHHb+RGsPbfwrQN+hKdCck/s=; b=Agr5gTRikfkoYk2fhSzNHz50EQzyhqUgywCNrIASzAx1QNOC7GI5N6wJjja1jhjZXW YErlYupY/6K1mZfST63hjDueE6DhRi4qMGxgzya5Cyt0xk65xoDczZlmKTwMH6dY6vD1 JqjVpTkgBpEVTdVWZL1wJGtBLhH67qHeaAo+87Ov9BrfzTw7GmWaXbLzxt/rHZG2xhd+ QRbU2uP+YCHSB+s0MNxibFpv2Jksdx70E/SIJbfrzFqaUJCt9+xj2+DWXjvQmOK10bUS D36oPfXo9PZEGAGrfK4yx/UHIJ/unVMswMKEW6sXt7nrFULDjIm0bQT866R17PjWu/Gr GApQ== X-Gm-Message-State: AFqh2kqDQCeJ9s8O46J3N4a0cFtz6blg3umuW+o4J1MjvMfg3w3hU1DR uG9M03xX3TQUXMVAWClQ+SI+rg== X-Google-Smtp-Source: AMrXdXuM12mBzocEhuMcUaHxAAUx1SH1UDETPNtrsDAD8zfD6TsTHXBUEAZtLnOMm8WCM7+fJN+OCQ== X-Received: by 2002:a05:6402:1854:b0:483:6039:9801 with SMTP id v20-20020a056402185400b0048360399801mr22324086edy.22.1672483680664; Sat, 31 Dec 2022 02:48:00 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-80-180-23-57.retail.telecomitalia.it. [80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.47.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:48:00 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 07/11] clk: imx: composite-8m: add device tree support Date: Sat, 31 Dec 2022 11:47:32 +0100 Message-Id: <20221231104736.12635-8-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221231_024803_092848_6B4153FB X-CRM114-Status: GOOD ( 14.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The patch, backwards compatible, extends the driver to initialize the clock directly from the device tree. Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk-composite-8m.c | 83 ++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index cbf0d7955a00..8c945d180318 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include #include "clk.h" @@ -25,6 +27,9 @@ #define PCG_CGC_SHIFT 28 +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -250,3 +255,81 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name, return ERR_CAST(hw); } EXPORT_SYMBOL_GPL(__imx8m_clk_hw_composite); + +static void __init _of_imx_composite_clk_setup(struct device_node *node, + u32 type) +{ + void __iomem *reg; + struct clk_hw *hw; + const char *name = node->name; + unsigned int num_parents; + const char **parent_names; + unsigned long flags = IMX_COMPOSITE_CLK_FLAGS_DEFAULT; + + reg = of_iomap(node, 0); + if (IS_ERR(reg)) { + pr_err("failed to get reg address for %pOFn\n", node); + return; + } + + num_parents = of_clk_get_parent_count(node); + if (num_parents < 2) { + pr_err("%pOFn must have parents\n", node); + return; + } + + parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); + if (!parent_names) + return; + + of_clk_parent_fill(node, parent_names, num_parents); + of_property_read_string(node, "clock-output-names", &name); + + if (of_property_read_bool(node, "fsl,get-rate-nocache")) + flags |= CLK_GET_RATE_NOCACHE; + + if (of_property_read_bool(node, "fsl,is-critical")) + flags |= CLK_IS_CRITICAL; + + hw = __imx8m_clk_hw_composite(name, parent_names, num_parents, reg, + type, flags); + if (!IS_ERR(hw)) + of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); + + kfree(parent_names); +} + +/** + * of_imx_composite_clk_setup() - Setup function for imx composite clock + * @node: device node for the clock + */ +void __init of_imx_composite_clk_setup(struct device_node *node) +{ + _of_imx_composite_clk_setup(node, IMX_COMPOSITE_CORE); +} +CLK_OF_DECLARE(fsl_composite_8m_clk, "fsl,imx8m-composite-clock", + of_imx_composite_clk_setup); + +/** + * of_imx_composite_bus_clk_setup() - Setup function for imx composite clock + * @node: device node for the clock + */ +void __init of_imx_composite_bus_clk_setup(struct device_node *node) +{ + _of_imx_composite_clk_setup(node, IMX_COMPOSITE_BUS); +} +CLK_OF_DECLARE(fsl_composite_bus_8m_clk, "fsl,imx8m-composite-bus-clock", + of_imx_composite_bus_clk_setup); + +/** + * of_imx_composite_fw_managed_clk_setup() - Setup function for imx + * composite fw managed clock + * @node: device node for the clock + */ +void __init of_imx_composite_fw_managed_clk_setup(struct device_node *node) +{ + _of_imx_composite_clk_setup(node, IMX_COMPOSITE_FW_MANAGED); +} +CLK_OF_DECLARE(fsl_composite_fw_managed_8m_clk, + "fsl,imx8m-composite-fw-managed-clock", + of_imx_composite_fw_managed_clk_setup);