From patchwork Fri Jan 6 16:37:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 13091561 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6DBEFC3DA7A for ; Fri, 6 Jan 2023 16:41:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=06tLzv6EZG/OrHBzkymR79AgFO490Gv72d+lHhG8l1Q=; b=GSqx3yfdEkNGtu msbR+w0L1KplKqriuBx34IHcImC1c6ocZ8ExqCajFKiUjhVWMrRvbAKwAaO69kwzwIGapI4pbafTN vpfOojUZxp5/sHdKapXPy/2MjBxf6BKqGxP32trA1CAtifDxUmg/bASOEsWAgmZQroACNBgDOQjVs Ray7lepKOOwdXUrWLgf0sTf23ftvW4KU+YRbRwnLRbUC3pb/29wjWSsXlthT8JWQreZgnWuVN6IOl CD6ptmgAnRf1XwBlglnjlDOTgXdtaZhj1avCwazK5E4LNlz2VjUguyaCW6Tcvrn1F+M0+4OjX4bmB OfoBMJmsWkfaJdtdlHdw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pDpls-00AKUu-2h; Fri, 06 Jan 2023 16:40:44 +0000 Received: from relay11.mail.gandi.net ([217.70.178.231]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pDpjR-00AHne-PQ for linux-arm-kernel@lists.infradead.org; Fri, 06 Jan 2023 16:38:15 +0000 Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id 09A49100004; Fri, 6 Jan 2023 16:38:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1673023092; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=za07u3am99m9O8qsvHnffjPQ4VUp9cGlF/y8sTJ/oEc=; b=UadNlEanFI/dCSWobeBNNUgZTNpR1IV9cLkljoUr2PkVozD+o5PLzlIoBwHHoO+hfsxV61 mNS4MSLlKQOVaapHK/Tjw2PaoIqFEav7FASYVVCfGX92s0fML1812FKzOB06TTljJ2wrDG m2Mnl9EeQ7r911JAciuI82VlSfryiysDkNoCCFztBPjI+65HiEnzWWqgZ2m4Kx6ZqwmQyp XSx8cvseZqAnzWThjWSy0d0OO3F01rmUHVA2AeKSbSFWfaqi0NFvL9cO9g9uaYCOQ9BmMd 11Gsi9Nt97tPS5mmzZd9t48iidHiua7ZVQUxuHLzBIVKGHrymMXBU7AJwSVrSg== From: Herve Codina To: Herve Codina , Li Yang , Rob Herring , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Christophe Leroy , Michael Ellerman , Nicholas Piggin , Qiang Zhao , Jaroslav Kysela , Takashi Iwai , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen Cc: linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni Subject: [PATCH v2 05/10] dt-bindings: soc: fsl: cpm_qe: Add QMC controller Date: Fri, 6 Jan 2023 17:37:41 +0100 Message-Id: <20230106163746.439717-6-herve.codina@bootlin.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230106163746.439717-1-herve.codina@bootlin.com> References: <20230106163746.439717-1-herve.codina@bootlin.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230106_083814_108506_456ED134 X-CRM114-Status: GOOD ( 15.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for the QMC (QUICC Multichannel Controller) available in some PowerQUICC SoC such as MPC885 or MPC866. Signed-off-by: Herve Codina --- .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 167 ++++++++++++++++++ 1 file changed, 167 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml new file mode 100644 index 000000000000..caf71f3a3f3f --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PowerQUICC CPM QUICC Multichannel Controller (QMC) + +maintainers: + - Herve Codina + +description: | + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within + one serial controller using the same TDM physical interface routed from + TSA. + +properties: + compatible: + items: + - enum: + - fsl,mpc885-scc-qmc + - fsl,mpc866-scc-qmc + - const: fsl,cpm1-scc-qmc + + reg: + items: + - description: SCC (Serial communication controller) register base + - description: SCC parameter ram base + - description: Dual port ram base + + reg-names: + items: + - const: scc_regs + - const: scc_pram + - const: dpram + + interrupts: + description: SCC interrupt line in the CPM interrupt controller + + fsl,cpm-command: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Cf. soc/fsl/cpm_qe/cpm.txt + + tsa: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the TSA + + tsa-cell-id: + enum: [1, 2, 3] + description: | + TSA cell ID (dt-bindings/soc/fsl-tsa.h defines these values) + - 1: SCC2 + - 2: SCC3 + - 3: SCC4 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#chan-cells': + const: 1 + +patternProperties: + "^channel@([0-9]|[1-5][0-9]|6[0-3])$": + description: + A channel managed by this controller + type: object + + properties: + reg: + minimum: 0 + maximum: 63 + description: + The channel number + + fsl,mode: + $ref: /schemas/types.yaml#/definitions/string + enum: [transparent, hdlc] + default: transparent + description: Operational mode + + fsl,reverse-data: + $ref: /schemas/types.yaml#/definitions/flag + description: + The bit order as seen on the channels is reversed, + transmitting/receiving the MSB of each octet first. + This flag is used only in 'transparent' mode. + + tx-ts-mask: + $ref: /schemas/types.yaml#/definitions/uint64 + description: + Channel assigned Tx time-slots within the Tx time-slots routed + by the TSA to this cell. + + rx-ts-mask: + $ref: /schemas/types.yaml#/definitions/uint64 + description: + Channel assigned Rx time-slots within the Rx time-slots routed + by the TSA to this cell. + + required: + - reg + - tx-ts-mask + - rx-ts-mask + +required: + - compatible + - reg + - reg-names + - interrupts + - tsa + - tsa-cell-id + - '#address-cells' + - '#size-cells' + - '#chan-cells' + +additionalProperties: false + +examples: + - | + #include + + scc_qmc@a60 { + compatible = "fsl,mpc885-scc-qmc", "fsl,cpm1-scc-qmc"; + reg = <0xa60 0x20>, + <0x3f00 0xc0>, + <0x2000 0x1000>; + reg-names = "scc_regs", "scc_pram", "dpram"; + interrupts = <27>; + interrupt-parent = <&CPM_PIC>; + fsl,cpm-command = <0xc0>; + + #address-cells = <1>; + #size-cells = <0>; + #chan-cells = <1>; + + tsa = <&tsa>; + tsa-cell-id = ; + + channel@16 { + /* Ch16 : First 4 even TS from all routed from TSA */ + reg = <16>; + fsl,mode = "transparent"; + fsl,reverse-data; + tx-ts-mask = <0x00000000 0x000000AA>; + rx-ts-mask = <0x00000000 0x000000AA>; + }; + + channel@17 { + /* Ch17 : First 4 odd TS from all routed from TSA */ + reg = <17>; + fsl,mode = "transparent"; + fsl,reverse-data; + tx-ts-mask = <0x00000000 0x00000055>; + rx-ts-mask = <0x00000000 0x00000055>; + }; + + channel@19 { + /* Ch19 : 8 TS (TS 8..15) from all routed from TSA */ + reg = <19>; + fsl,mode = "hdlc"; + tx-ts-mask = <0x00000000 0x0000FF00>; + rx-ts-mask = <0x00000000 0x0000FF00>; + }; + };