From patchwork Mon Jan 9 23:43:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yabin Cui X-Patchwork-Id: 13094531 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D69A4C5479D for ; Mon, 9 Jan 2023 23:44:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: Mime-Version:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=xhc78DhuCJZIu1glJhGyzBxkvvcglHsWCqardlEWxPU=; b=4CC QuvDazeXY3Go8M0J41kmU2or+ReVZIu41T0THVA9IqfbX8FAB3/ukQJVF8aFq1AiFRuV23Zoqmnlf y1dN9hAJA0MbWWPXo4ju26y0Pg0Xrkib01ddmSGJ1pvae7QJWmV6EX6kgArjK0ZmRa67DnplzQbNs hDfyAcntqb5kriv32kRMfp/WBFzX4f7HMCcSnQda8RN9bI2o1BRDuysoo4ozdQLdf1G+Q+rDgvhmS +OFK9UU/VfauZ3tN7TUdp22VMElNvAgwm52Xpv89Y8h/NZ4bkljlKCmgZlM9cYBa3fH7HRQcMcKjD rSdLVlDV+lzt+HVJXK30Dp9tuQnMlQA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pF1nX-004eU7-2D; Mon, 09 Jan 2023 23:43:23 +0000 Received: from mail-pj1-x104a.google.com ([2607:f8b0:4864:20::104a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pF1nU-004eT5-0z for linux-arm-kernel@lists.infradead.org; Mon, 09 Jan 2023 23:43:21 +0000 Received: by mail-pj1-x104a.google.com with SMTP id kk14-20020a17090b4a0e00b00226f5087f41so2441882pjb.3 for ; Mon, 09 Jan 2023 15:43:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:message-id:mime-version:date:from:to:cc:subject :date:message-id:reply-to; bh=FJqodOVZ3N83/BqsgJaqpNXe1RkJlGSQQAWmq9op64U=; b=T9qbe/GuQxKBRu1v0S/FfY2XTEaEQzUmiO4VhaVhoSt+YjxMec+P2RIRQwmD2ZxObM m+o6s+0/2L/UBGkzH46WN0vcByupJvxQJFYvDNgNkzAkr+1l0aAPSDKAJGJga0vyIYmA iKFeN8YqnxfvnOsDJoc6AOmKJa9QG/TflLnM4yH29/zmNzw3GJNCoeOjJoEgkRQ4hOsI IvogbotG3D2+h4SkOWIVPk+o6KV1EP2QmqJ9slT5MFf9PPQtp98EkjsXEV1kLYcUr3Uu 1EN9Aqeyy81zW3fChcIKGJsnMQdND5TLryZ3hHzpmD9/8orCqFSxJXVZPq2S1rMgmF4S stKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:message-id:mime-version:date:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=FJqodOVZ3N83/BqsgJaqpNXe1RkJlGSQQAWmq9op64U=; b=rIju5uePVYT79rTAmrnjLPPh/RHy9eZcJioSHinzLC9vlr7kIlHw16df+hqGx3Dujd A4lTnGG/DDKtkJ1x5Pc25AsyB7eVS54L+90CtQNxSEJmW0afLFzHJFHHHW0CCW6FyMjT roGwz7hh34v8WIhN5dOIjCJqzFAkGc3/vH05ZqrfBd738eU1GK1ytkYNiSn3kA7hNFs8 RjkD5C6SrHGbECs6qpAzyKM+0zUERfLIUo4IoL5xoFbGTHx+pxI0POpV6s5ydyT6dGka KXENOkjI5Zn0dRd0qEaD2i8y0ucujSS5hJAV9KQ/iXMD1XIMP2mWzz2+MnRx4mbUoYAs IEGw== X-Gm-Message-State: AFqh2kodOIcEsdeaNBxlpyCGyiZcsu2et2EneyV0xEf7IvL/Rv9zA9DA 2lLwcz8Qq408PZWeOka7P8ETWWt4nw== X-Google-Smtp-Source: AMrXdXsLWu88orFDYRQBDp4f7C2u/Chbt1axITWfT9KYKOeJ2E9zlZn9urjdaUUZAeDv6tZVY9kgNu5M+6k= X-Received: from yabinc3.c.googlers.com ([fda3:e722:ac3:cc00:24:72f4:c0a8:1274]) (user=yabinc job=sendgmr) by 2002:a17:902:ef45:b0:189:1318:714 with SMTP id e5-20020a170902ef4500b0018913180714mr5048085plx.122.1673307795909; Mon, 09 Jan 2023 15:43:15 -0800 (PST) Date: Mon, 9 Jan 2023 23:43:12 +0000 Mime-Version: 1.0 X-Mailer: git-send-email 2.39.0.314.g84b9a713c41-goog Message-ID: <20230109234312.2870846-1-yabinc@google.com> Subject: [PATCH] coresight: tmc-etr: Don't enable ETR when it's not ready From: Yabin Cui To: Mathieu Poirier , Suzuki K Poulose , Mike Leach , Leo Yan Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yabin Cui X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230109_154320_107019_A75A02E5 X-CRM114-Status: GOOD ( 15.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Otherwise, it may cause error in AXI bus and result in a kernel panic. Signed-off-by: Yabin Cui --- .../hwtracing/coresight/coresight-tmc-core.c | 4 +++- .../hwtracing/coresight/coresight-tmc-etr.c | 18 +++++++++++++++--- drivers/hwtracing/coresight/coresight-tmc.h | 2 +- 3 files changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index 07abf28ad725..c106d142e632 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -31,7 +31,7 @@ DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr"); -void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) +int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) { struct coresight_device *csdev = drvdata->csdev; struct csdev_access *csa = &csdev->access; @@ -40,7 +40,9 @@ void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) if (coresight_timeout(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) { dev_err(&csdev->dev, "timeout while waiting for TMC to be Ready\n"); + return -EBUSY; } + return 0; } void tmc_flush_and_stop(struct tmc_drvdata *drvdata) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 867ad8bb9b0c..2da99dd41ed6 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -983,15 +983,21 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata) etr_buf->ops->sync(etr_buf, rrp, rwp); } -static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) +static int __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) { u32 axictl, sts; struct etr_buf *etr_buf = drvdata->etr_buf; + int rc = 0; CS_UNLOCK(drvdata->base); /* Wait for TMCSReady bit to be set */ - tmc_wait_for_tmcready(drvdata); + rc = tmc_wait_for_tmcready(drvdata); + if (rc) { + dev_err(&drvdata->csdev->dev, "not ready ETR isn't enabled\n"); + CS_LOCK(drvdata->base); + return rc; + } writel_relaxed(etr_buf->size / 4, drvdata->base + TMC_RSZ); writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE); @@ -1032,6 +1038,7 @@ static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) tmc_enable_hw(drvdata); CS_LOCK(drvdata->base); + return rc; } static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata, @@ -1060,7 +1067,12 @@ static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata, rc = coresight_claim_device(drvdata->csdev); if (!rc) { drvdata->etr_buf = etr_buf; - __tmc_etr_enable_hw(drvdata); + rc = __tmc_etr_enable_hw(drvdata); + if (rc) { + drvdata->etr_buf = NULL; + coresight_disclaim_device(drvdata->csdev); + tmc_etr_disable_catu(drvdata); + } } return rc; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 66959557cf39..01c0382a29c0 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -255,7 +255,7 @@ struct tmc_sg_table { }; /* Generic functions */ -void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); +int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); void tmc_flush_and_stop(struct tmc_drvdata *drvdata); void tmc_enable_hw(struct tmc_drvdata *drvdata); void tmc_disable_hw(struct tmc_drvdata *drvdata);