| Message ID | 20230110125101.10533-1-hejunhao3@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | coresight: etm4x: Fix accesses to TRCSEQRSTEVR and TRCSEQSTR | expand |
On Tue, 10 Jan 2023 at 12:51, Junhao He <hejunhao3@huawei.com> wrote: > > The TRCSEQRSTEVR and TRCSEQSTR register is not implemented if the > TRCIDR5.NUMSEQSTATE == 0. Skip accessing the register in such cases. > > Signed-off-by: Junhao He <hejunhao3@huawei.com> > --- > .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++++------ > 1 file changed, 12 insertions(+), 6 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 80fefaba58ee..c7a65d1524fc 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -424,8 +424,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); > for (i = 0; i < drvdata->nrseqstate - 1; i++) > etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); > - etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); > - etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); > + if (drvdata->nrseqstate) { > + etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); > + etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); > + } > etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); > for (i = 0; i < drvdata->nr_cntr; i++) { > etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); > @@ -1631,8 +1633,10 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) > for (i = 0; i < drvdata->nrseqstate - 1; i++) > state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); > > - state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); > - state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); > + if (drvdata->nrseqstate) { > + state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); > + state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); > + } > state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) { > @@ -1760,8 +1764,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) > for (i = 0; i < drvdata->nrseqstate - 1; i++) > etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); > > - etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); > - etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); > + if (drvdata->nrseqstate) { > + etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); > + etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); > + } > etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) { > -- > 2.33.0 > > _______________________________________________ > CoreSight mailing list -- coresight@lists.linaro.org > To unsubscribe send an email to coresight-leave@lists.linaro.org Reviewed-by: Mike Leach <mike.leach@linaro.org>
On 10/01/2023 12:51, Junhao He wrote: > The TRCSEQRSTEVR and TRCSEQSTR register is not implemented if the > TRCIDR5.NUMSEQSTATE == 0. Skip accessing the register in such cases. > > Signed-off-by: Junhao He <hejunhao3@huawei.com> This must have : Fixes: 2e1cdfe184b5 ("coresight-etm4x: Adding CoreSight ETM4x driver") The patch as such looks correct to me. I will queue this. Thanks Suzuki > --- > .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++++------ > 1 file changed, 12 insertions(+), 6 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 80fefaba58ee..c7a65d1524fc 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -424,8 +424,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); > for (i = 0; i < drvdata->nrseqstate - 1; i++) > etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); > - etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); > - etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); > + if (drvdata->nrseqstate) { > + etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); > + etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); > + } > etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); > for (i = 0; i < drvdata->nr_cntr; i++) { > etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); > @@ -1631,8 +1633,10 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) > for (i = 0; i < drvdata->nrseqstate - 1; i++) > state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); > > - state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); > - state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); > + if (drvdata->nrseqstate) { > + state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); > + state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); > + } > state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) { > @@ -1760,8 +1764,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) > for (i = 0; i < drvdata->nrseqstate - 1; i++) > etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); > > - etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); > - etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); > + if (drvdata->nrseqstate) { > + etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); > + etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); > + } > etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) {
On 1/10/23 18:21, Junhao He wrote: > The TRCSEQRSTEVR and TRCSEQSTR register is not implemented if the s/register is/registers are/ > TRCIDR5.NUMSEQSTATE == 0. Skip accessing the register in such cases. s/register/registers/ > > Signed-off-by: Junhao He <hejunhao3@huawei.com> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> > --- > .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++++------ > 1 file changed, 12 insertions(+), 6 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 80fefaba58ee..c7a65d1524fc 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -424,8 +424,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); > for (i = 0; i < drvdata->nrseqstate - 1; i++) > etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); > - etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); > - etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); > + if (drvdata->nrseqstate) { > + etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); > + etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); > + } > etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); > for (i = 0; i < drvdata->nr_cntr; i++) { > etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); > @@ -1631,8 +1633,10 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) > for (i = 0; i < drvdata->nrseqstate - 1; i++) > state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); > > - state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); > - state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); > + if (drvdata->nrseqstate) { > + state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); > + state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); > + } > state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) { > @@ -1760,8 +1764,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) > for (i = 0; i < drvdata->nrseqstate - 1; i++) > etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); > > - etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); > - etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); > + if (drvdata->nrseqstate) { > + etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); > + etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); > + } > etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) {
On 2023/1/12 11:48, Anshuman Khandual wrote: > > On 1/10/23 18:21, Junhao He wrote: >> The TRCSEQRSTEVR and TRCSEQSTR register is not implemented if the > s/register is/registers are/ Ok, will fix it. Thanks. >> TRCIDR5.NUMSEQSTATE == 0. Skip accessing the register in such cases. > s/register/registers/ Ok, will fix it. Thanks. >> Signed-off-by: Junhao He <hejunhao3@huawei.com> > Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> > >> --- >> .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++++------ >> 1 file changed, 12 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> index 80fefaba58ee..c7a65d1524fc 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> @@ -424,8 +424,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) >> etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); >> for (i = 0; i < drvdata->nrseqstate - 1; i++) >> etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); >> - etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); >> - etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); >> + if (drvdata->nrseqstate) { >> + etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); >> + etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); >> + } >> etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); >> for (i = 0; i < drvdata->nr_cntr; i++) { >> etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); >> @@ -1631,8 +1633,10 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) >> for (i = 0; i < drvdata->nrseqstate - 1; i++) >> state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); >> >> - state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); >> - state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); >> + if (drvdata->nrseqstate) { >> + state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); >> + state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); >> + } >> state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); >> >> for (i = 0; i < drvdata->nr_cntr; i++) { >> @@ -1760,8 +1764,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) >> for (i = 0; i < drvdata->nrseqstate - 1; i++) >> etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); >> >> - etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); >> - etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); >> + if (drvdata->nrseqstate) { >> + etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); >> + etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); >> + } >> etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); >> >> for (i = 0; i < drvdata->nr_cntr; i++) { > . >
On 2023/1/11 0:15, Suzuki K Poulose wrote: > > On 10/01/2023 12:51, Junhao He wrote: >> The TRCSEQRSTEVR and TRCSEQSTR register is not implemented if the >> TRCIDR5.NUMSEQSTATE == 0. Skip accessing the register in such cases. >> >> Signed-off-by: Junhao He <hejunhao3@huawei.com> > > This must have : > > Fixes: 2e1cdfe184b5 ("coresight-etm4x: Adding CoreSight ETM4x driver") > > The patch as such looks correct to me. > > I will queue this. > > Thanks > Suzuki Sure, Will fix in next version. Best regards, Junhao. > >> --- >> .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++++------ >> 1 file changed, 12 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c >> b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> index 80fefaba58ee..c7a65d1524fc 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> @@ -424,8 +424,10 @@ static int etm4_enable_hw(struct etmv4_drvdata >> *drvdata) >> etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); >> for (i = 0; i < drvdata->nrseqstate - 1; i++) >> etm4x_relaxed_write32(csa, config->seq_ctrl[i], >> TRCSEQEVRn(i)); >> - etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); >> - etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); >> + if (drvdata->nrseqstate) { >> + etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); >> + etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); >> + } >> etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); >> for (i = 0; i < drvdata->nr_cntr; i++) { >> etm4x_relaxed_write32(csa, config->cntrldvr[i], >> TRCCNTRLDVRn(i)); >> @@ -1631,8 +1633,10 @@ static int __etm4_cpu_save(struct >> etmv4_drvdata *drvdata) >> for (i = 0; i < drvdata->nrseqstate - 1; i++) >> state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); >> - state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); >> - state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); >> + if (drvdata->nrseqstate) { >> + state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); >> + state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); >> + } >> state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); >> for (i = 0; i < drvdata->nr_cntr; i++) { >> @@ -1760,8 +1764,10 @@ static void __etm4_cpu_restore(struct >> etmv4_drvdata *drvdata) >> for (i = 0; i < drvdata->nrseqstate - 1; i++) >> etm4x_relaxed_write32(csa, state->trcseqevr[i], >> TRCSEQEVRn(i)); >> - etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); >> - etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); >> + if (drvdata->nrseqstate) { >> + etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); >> + etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); >> + } >> etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); >> for (i = 0; i < drvdata->nr_cntr; i++) { > > _______________________________________________ > CoreSight mailing list -- coresight@lists.linaro.org > To unsubscribe send an email to coresight-leave@lists.linaro.org > > . >
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 80fefaba58ee..c7a65d1524fc 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -424,8 +424,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); for (i = 0; i < drvdata->nrseqstate - 1; i++) etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); - etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); - etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); + if (drvdata->nrseqstate) { + etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); + etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); + } etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); for (i = 0; i < drvdata->nr_cntr; i++) { etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); @@ -1631,8 +1633,10 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) for (i = 0; i < drvdata->nrseqstate - 1; i++) state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); - state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); - state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); + if (drvdata->nrseqstate) { + state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); + state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); + } state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); for (i = 0; i < drvdata->nr_cntr; i++) { @@ -1760,8 +1764,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) for (i = 0; i < drvdata->nrseqstate - 1; i++) etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); - etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); - etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); + if (drvdata->nrseqstate) { + etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); + etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); + } etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); for (i = 0; i < drvdata->nr_cntr; i++) {
The TRCSEQRSTEVR and TRCSEQSTR register is not implemented if the TRCIDR5.NUMSEQSTATE == 0. Skip accessing the register in such cases. Signed-off-by: Junhao He <hejunhao3@huawei.com> --- .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-)