From patchwork Mon Jan 16 23:52:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 13103972 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6FB19C54EBE for ; Mon, 16 Jan 2023 23:54:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=7mRLYXAuUFLC9f5s/nshrZqEyLZ50e4hzWGoqYK0NO4=; b=EEYrOzA2ka+wFG mkEm0aCzao1uDEkviENdCt/86BTKyqorMJN6b73rqLZv+HnZsUs/AyEyLb08x2sQr5O2h9UElJwPS vPiPuEtv/0AkVZVVgjBhkME5aQPNgwfE3IobGTZfJ4BQCGh7zUG9itOOL6S7vOmlMTd/7/H8JnoV7 lWFRCJ1z57tEPPC+u4aM0kxyQaKGj6P/7UXj83KNOH1sItcVAtvfgcevA7LSrl95Gv3EYuvlPlq/2 9QszTPgKtSH84ajZbt42x7znE/l1ijTbq2e9GwEjSE2LSMf9Qn+X0903QowEIxb/TiW07GoRhChOV t6wCGPYINq7s8B3F/VkA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pHZHa-00CIEm-8v; Mon, 16 Jan 2023 23:52:54 +0000 Received: from 0001.3ffe.de ([159.69.201.130] helo=mail.3ffe.de) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pHZHW-00CICu-OG; Mon, 16 Jan 2023 23:52:52 +0000 Received: from mwalle01.sab.local (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.3ffe.de (Postfix) with ESMTPSA id D81451645; Tue, 17 Jan 2023 00:52:45 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2022082101; t=1673913166; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qrw3VdQJ88seeNfsCmHZ0Ug/EiNIUO7V5SWjfSjWOKQ=; b=rvBx26LB/U/ku27CC+lu1uAY7KDI3oh4SWNBjiMZKuPQB+vluqypoYHhh5/2/VukYWWUlc UT7lV2rpdokc5dCe1bAjyAZtkHwq8etN0SQsfmTRnLepJAbIYpc6feOCz4+pNTSiWpzhn8 IHadilsFnOnfAEsWsBPVi+83xk/a5TeB1rOgjQfqySx9PDK2/QQ3m6Ao35i2v3GGXy4iYp Wjwk75qQuCMUwq8PSkAVJFdPd0mgfRA5PJlGfZ9KfhJlVZU4lX0g/tWza991VE/YnhVlVa /CyBLp1jcHEkB1AwLQMAdwxpXE3r6i4YX3YA1GEqJXimD20zJljhis3cRes2Zw== From: Michael Walle Date: Tue, 17 Jan 2023 00:52:18 +0100 Subject: [PATCH net-next 03/12] net: nixge: Separate C22 and C45 transactions MIME-Version: 1.0 Message-Id: <20230116-net-next-c45-seperation-part-3-v1-3-0c53afa56aad@walle.cc> References: <20230116-net-next-c45-seperation-part-3-v1-0-0c53afa56aad@walle.cc> In-Reply-To: <20230116-net-next-c45-seperation-part-3-v1-0-0c53afa56aad@walle.cc> To: Sean Wang , Landen Chao , DENG Qingfang , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , Russell King , Byungho An , Nicolas Ferre , Claudiu Beznea , Jesse Brandeburg , Tony Nguyen , Yisen Zhuang , Salil Mehta , Tom Lendacky , Shyam Sundar S K , Sergey Shtylyov Cc: netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, intel-wired-lan@lists.osuosl.org, linux-renesas-soc@vger.kernel.org, Andrew Lunn , Michael Walle X-Mailer: b4 0.11.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230116_155251_010472_46D33DA1 X-CRM114-Status: GOOD ( 14.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Andrew Lunn The nixge MDIO bus driver can perform both C22 and C45 transfers. Create separate functions for each and register the C45 versions using the new API calls where appropriate. Signed-off-by: Andrew Lunn Signed-off-by: Michael Walle --- drivers/net/ethernet/ni/nixge.c | 141 ++++++++++++++++++++++++---------------- 1 file changed, 85 insertions(+), 56 deletions(-) diff --git a/drivers/net/ethernet/ni/nixge.c b/drivers/net/ethernet/ni/nixge.c index 62320be4de5a..56e02cba0b8a 100644 --- a/drivers/net/ethernet/ni/nixge.c +++ b/drivers/net/ethernet/ni/nixge.c @@ -1081,40 +1081,59 @@ static const struct ethtool_ops nixge_ethtool_ops = { .get_link = ethtool_op_get_link, }; -static int nixge_mdio_read(struct mii_bus *bus, int phy_id, int reg) +static int nixge_mdio_read_c22(struct mii_bus *bus, int phy_id, int reg) { struct nixge_priv *priv = bus->priv; u32 status, tmp; int err; u16 device; - if (reg & MII_ADDR_C45) { - device = (reg >> 16) & 0x1f; + device = reg & 0x1f; - nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff); + tmp = NIXGE_MDIO_CLAUSE22 | NIXGE_MDIO_OP(NIXGE_MDIO_C22_READ) | + NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device); - tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_OP_ADDRESS) - | NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device); + nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp); + nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1); - nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp); - nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1); + err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status, + !status, 10, 1000); + if (err) { + dev_err(priv->dev, "timeout setting read command"); + return err; + } - err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status, - !status, 10, 1000); - if (err) { - dev_err(priv->dev, "timeout setting address"); - return err; - } + status = nixge_ctrl_read_reg(priv, NIXGE_REG_MDIO_DATA); - tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_C45_READ) | - NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device); - } else { - device = reg & 0x1f; + return status; +} - tmp = NIXGE_MDIO_CLAUSE22 | NIXGE_MDIO_OP(NIXGE_MDIO_C22_READ) | - NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device); +static int nixge_mdio_read_c45(struct mii_bus *bus, int phy_id, int device, + int reg) +{ + struct nixge_priv *priv = bus->priv; + u32 status, tmp; + int err; + + nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff); + + tmp = NIXGE_MDIO_CLAUSE45 | + NIXGE_MDIO_OP(NIXGE_MDIO_OP_ADDRESS) | + NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device); + + nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp); + nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1); + + err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status, + !status, 10, 1000); + if (err) { + dev_err(priv->dev, "timeout setting address"); + return err; } + tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_C45_READ) | + NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device); + nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp); nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1); @@ -1130,57 +1149,65 @@ static int nixge_mdio_read(struct mii_bus *bus, int phy_id, int reg) return status; } -static int nixge_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val) +static int nixge_mdio_write_c22(struct mii_bus *bus, int phy_id, int reg, + u16 val) { struct nixge_priv *priv = bus->priv; u32 status, tmp; u16 device; int err; - if (reg & MII_ADDR_C45) { - device = (reg >> 16) & 0x1f; + device = reg & 0x1f; - nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff); + tmp = NIXGE_MDIO_CLAUSE22 | NIXGE_MDIO_OP(NIXGE_MDIO_C22_WRITE) | + NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device); - tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_OP_ADDRESS) - | NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device); + nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val); + nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp); + nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1); - nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp); - nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1); + err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status, + !status, 10, 1000); + if (err) + dev_err(priv->dev, "timeout setting write command"); - err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status, - !status, 10, 1000); - if (err) { - dev_err(priv->dev, "timeout setting address"); - return err; - } + return err; +} - tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_C45_WRITE) - | NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device); +static int nixge_mdio_write_c45(struct mii_bus *bus, int phy_id, + int device, int reg, u16 val) +{ + struct nixge_priv *priv = bus->priv; + u32 status, tmp; + int err; - nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val); - nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp); - err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status, - !status, 10, 1000); - if (err) - dev_err(priv->dev, "timeout setting write command"); - } else { - device = reg & 0x1f; + nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff); - tmp = NIXGE_MDIO_CLAUSE22 | - NIXGE_MDIO_OP(NIXGE_MDIO_C22_WRITE) | - NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device); + tmp = NIXGE_MDIO_CLAUSE45 | + NIXGE_MDIO_OP(NIXGE_MDIO_OP_ADDRESS) | + NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device); - nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val); - nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp); - nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1); + nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp); + nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1); - err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status, - !status, 10, 1000); - if (err) - dev_err(priv->dev, "timeout setting write command"); + err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status, + !status, 10, 1000); + if (err) { + dev_err(priv->dev, "timeout setting address"); + return err; } + tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_C45_WRITE) | + NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device); + + nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val); + nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp); + + err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status, + !status, 10, 1000); + if (err) + dev_err(priv->dev, "timeout setting write command"); + return err; } @@ -1195,8 +1222,10 @@ static int nixge_mdio_setup(struct nixge_priv *priv, struct device_node *np) snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(priv->dev)); bus->priv = priv; bus->name = "nixge_mii_bus"; - bus->read = nixge_mdio_read; - bus->write = nixge_mdio_write; + bus->read = nixge_mdio_read_c22; + bus->write = nixge_mdio_write_c22; + bus->read_c45 = nixge_mdio_read_c45; + bus->write_c45 = nixge_mdio_write_c45; bus->parent = priv->dev; priv->mii_bus = bus;