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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: GoUxlm49HtaVXAY5j6tlkwI/1hp/4p/K5FQDNk05SivFVy2YAEl78IDNu/rBIcNtEIz69az93rajJqwZxmxrW2d3EJS33aSFTOIjxhDWlYUpqkV5eQ0nMWhvlqy+1F9WxGfsA7RDkfNOQC9sN0cE79MjrAN5hVI9MvibT34aOZVqaApAB2/B5KqC2QOxnTNXzhh54ckg6W9AoTG+o0FO5EHBtN35SnctGKXo7A2n8WABsQywiwKAf7tasBdxJIvQKRZffKbNy+UlEPJQZPdd4cTh1K63+XEESwg8iP7Zsh4Eoyz3Y/RqjRDsdjJA2imJN6ZAKiKJKpKHDCoRKI5Iuq7GjN2J2Exd6k84DHO7Q4X6NZtduze1LZiFZXnDti/f5hVOHDXt+3b8i8mY5ipt4A0QPYM8PxWrZscBFmJ4B4l06teePkIAuuhtRWEd2jdSEot+zIRVPUgAQSGQIifdGRy4iGKNHtb/dPBwB+M3lcesDMEDXmLElSL6lHInCS7kaAA86TU9abTsij6jzqN1O12vWoFoVABdDmIg4wFPwrWFrIqra0j4fKclWx8Ik1c298AFvA/uelL3wl9drV2yxZZIIrP5BADO6RRIb/B8VoRncN5H0gue2+tIyVe52CvOsdTYQq0+B/HAq0pVWYUEbJpnCthZF0KcTj6qKi1GMn3ffLO4tg3Zddf/b7MsymD11ma4PzpPHgBMm+1Rdtz20OAur2/KESmn0Cq3Fm3VDyqQqwVI5o1hHc7MB19L30e1kvecew/hj0d7KsgkvEm4cG6QJ38x7RvERAyi801YLAwEWZiIZt/8d+5wIT9XdwAuDSixxGDcDotUR1POKt8VNloszeBooxQy8GDgke7I5/l5NyVBkbJd7/K38GGy/ERdBOORpETbf9rHgwAbiludX4rwPE1sxSgMpa9icvzTeyIAZtvtV4QmA/w3GzbOVzYJL5IokXAzyZXrmlLUwo6eRFvchmFRQ1wel56aYPHH1XpTPfXyCr34ZLWyQWVFTKLg+WLhEe66J2yeY6xvDKYoz2PpWwiQ8L8bA5KqfGnOqmFK0HAUNdSeP4yqOGO2FdWBOfMeM2eFn1gCnt5DxSf5xBBZEHZBHry1DLLdN55j/HUiSk+WFnDWZYm8aGBb9qJvVXUegnaKuU25c/v5DHXOXiRfL0b3iWCy8pfGYk3w/k5BqOd5br7s+F3nnQrhA04ELGu2EtAxeVLMA0X6JSnU2ChywIRcVXVd0WlzdT8ka3fT4TNMH2x0Jgh/tzWQ43tLqRx9Kc1Jn4JEINqg3wQWpTDiKCm/6hOdXaLaDFp99qkB5KzRy5D4KxzK12GvPDtCLFpcy0G+gosP6jd9GTru0hkSJYT7JE3LsJ1LZ7Ot6L5CleGOvAUG3Jj/FFr1p1Zo8mNmI15x8zs2ce5yqx4aJYJiu1MFKl3/PolpI6vbrr6XfawZfNkxEIxhCNT5CEJBEHDygIawmFU2zzkpeAUjn6HbAzStdEakWjlVhRv2h8NGTcThIacuv+zx81JqFebyRgaWqDaL9UJWJfo2jo7ONquG25VPQ46aCEgsbP7OF4Rj17jvXXYSa64xqITEZ08QODRz5igZny5HZzevVBiJdGSnIpbRNmikUVZskKpe8hEeEnkT1i8KTcrupntv5YO89GS/xcvoVxVz7FVGocQtTnkmR/6fiOePIkbKhe72C6U= X-OriginatorOrg: wolfvision.net X-MS-Exchange-CrossTenant-Network-Message-Id: 1a760ca2-9af5-4b15-c985-08dafa2afa2d X-MS-Exchange-CrossTenant-AuthSource: DU0PR08MB9155.eurprd08.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2023 14:39:32.0158 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: e94ec9da-9183-471e-83b3-51baa8eb804f X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: G11G/7V5RklqhxwaG0Bixy7epljYqDrP1qaRaetJZzrgY0B4yUIXwtJW8KtBe5vdA+TsNnl5CeGPRAD6SxQlYhe8qQ6rmtRH7Xyai34GFRg= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB6556 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230119_063943_113126_22D7DC4F X-CRM114-Status: GOOD ( 20.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Rockchip VOP2 features an internal RGB output block, which can be attached to the video port 2 of the VOP2. Add support for this output block. Signed-off-by: Michael Riesch --- v2: - move away from wrong assumption that the RGB block is always connected to video port 2 -> check devicetree to find RGB block drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 44 ++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 06fcdfa7b885..f30037d161ae 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -39,6 +39,7 @@ #include "rockchip_drm_gem.h" #include "rockchip_drm_fb.h" #include "rockchip_drm_vop2.h" +#include "rockchip_rgb.h" /* * VOP2 architecture @@ -212,6 +213,9 @@ struct vop2 { struct clk *hclk; struct clk *aclk; + /* optional internal rgb encoder */ + struct rockchip_rgb *rgb; + /* must be put at the end of the struct */ struct vop2_win win[]; }; @@ -2393,6 +2397,25 @@ static void vop2_destroy_crtcs(struct vop2 *vop2) } } +static int vop2_find_rgb_encoder(struct vop2 *vop2) +{ + struct device_node *node = vop2->dev->of_node; + struct device_node *endpoint; + int i; + + for (i = 0; i < vop2->data->nr_vps; i++) { + endpoint = of_graph_get_endpoint_by_regs(node, i, + ROCKCHIP_VOP2_EP_RGB0); + if (!endpoint) + continue; + + of_node_put(endpoint); + return i; + } + + return -ENOENT; +} + static struct reg_field vop2_cluster_regs[VOP2_WIN_MAX_REG] = { [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 0, 0), [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 1, 5), @@ -2698,11 +2721,29 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) if (ret) return ret; + ret = vop2_find_rgb_encoder(vop2); + if (ret > 0) { + vop2->rgb = rockchip_rgb_init(dev, &vop2->vps[ret].crtc, + vop2->drm, ret); + if (IS_ERR(vop2->rgb)) { + if (PTR_ERR(vop2->rgb) == -EPROBE_DEFER) { + ret = PTR_ERR(vop2->rgb); + goto err_crtcs; + } + vop2->rgb = NULL; + } + } + rockchip_drm_dma_init_device(vop2->drm, vop2->dev); pm_runtime_enable(&pdev->dev); return 0; + +err_crtcs: + vop2_destroy_crtcs(vop2); + + return ret; } static void vop2_unbind(struct device *dev, struct device *master, void *data) @@ -2711,6 +2752,9 @@ static void vop2_unbind(struct device *dev, struct device *master, void *data) pm_runtime_disable(dev); + if (vop2->rgb) + rockchip_rgb_fini(vop2->rgb); + vop2_destroy_crtcs(vop2); }