From patchwork Tue Jan 24 10:56:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Etienne Carriere X-Patchwork-Id: 13113875 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9E447C25B4E for ; Tue, 24 Jan 2023 12:01:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=d3K2lg2m3J98x2TecVR2d7TX4LalI5aq5MTwnwHYIAQ=; b=ZmvOr15NnlH/aN M8hNouLCy/VEMiZ7Z8lZtb3Czj2NKtXQVw5cnIlNdJYvvOxSqCF5ZriYB1VF4Qjew0QslcNZaiEPq P3o/HorfXYQY+D83vVCIK+0HM0OTxxgjU5n82I8mvVd+RukVZte1ugyelBO9x1bWR6KdDbZeLXqbC By2vEeio9AWjSbZzz78IQRNw/L1pEWMfg+bwRfqXQK/coTAQwmcpbmBdWkz+gBMA+FoZMESqiSTKn xfqvjzviAge7ouWOOV6c/af+SL2B6ZRzzr/4FdAs994DxOtv7Vu+2sVm1kmVwP4nurnngJwflh9KA RJn+0HAOaztFWny0ZzYw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pKHyf-003b99-TR; Tue, 24 Jan 2023 12:00:38 +0000 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pKGz0-003HYI-Lk for linux-arm-kernel@lists.infradead.org; Tue, 24 Jan 2023 10:56:56 +0000 Received: by mail-wr1-x430.google.com with SMTP id q5so8809877wrv.0 for ; Tue, 24 Jan 2023 02:56:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=m7zN4CDUViF3PTZLyM/3kFec4UidZAgrawq/W4v1dbE=; b=SVJXlXmbWCgWfJoKLOELiV3fZM7TPGBX7/4aB4cChDFmAvaO9yCbZCWDpOcBZqJxaR KjIFa5J7OWQxCCSQRDc4f1OIGR1hBaWUF078zeJ8y/lM05hTyPeezt5abkzBoaOKnmlu jTa3bmaeBNjpSZvnrIm15snup4RRtZNHZRf+yM0ZEJLZ1KaCqFHbkBDp5ZjlGQzmCH8A q0EIoCrh1pgKipIQ3BjEfUn5cTeCRq4Y6O/7IbwYqJtXjpKZzSO132hhx609ae1/jmmp vYKvjj1A9a3WC4y57svKbk834PKkeoAJShWJsTjeUzT3yCJWhS2HJpTGcAeo11cyvoMc sAzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=m7zN4CDUViF3PTZLyM/3kFec4UidZAgrawq/W4v1dbE=; b=S/d6zu0NNsLJxvyDTeWyn4e0FnmEWKAnnvYkd1xBFh/a+lU8eZEhpqGQPtnAz6nJ5F 7oNA0auTSJMDQFmziUmg5xxhzseb4K2il0Jw6YJ8bMHWfj+QPD7j0sUTbm87IUwl0RU+ cvZqxdsmUoMshvUEZYOrYJY/sUCKY3iqYbs1kBR8sj04Od7SnM0/jGhrgnA63sVypqqq dLyf/GCBbJPa0b8z6MiU1Lyi6/n4UQ+eKMwMpuh4Yq+l1aavYMb8pj0obqodCt/Lk+L6 sp0lBRBFVKhOV8CgYs+8I8KU58iRn1JRjgSj5IbWjwBn9U+HWKTwgAImRJNo7twg/ig0 oKwQ== X-Gm-Message-State: AFqh2kpaHtXWd6vRL1k8QfVZRV8/IwpBFxsRFZol7Nswq8T7/zBUv+Hi NTAmBYPhT1+tgQPiecnfbE6xBQ== X-Google-Smtp-Source: AMrXdXu3Gr2Q/6kcZgUwMrG1H6sh7LLL+2/5nXY5yhzNItteTHxFz+SnPxHNUrK4wfxe4jmV40aS6Q== X-Received: by 2002:adf:e587:0:b0:2be:54a7:2b8b with SMTP id l7-20020adfe587000000b002be54a72b8bmr14573243wrm.21.1674557813173; Tue, 24 Jan 2023 02:56:53 -0800 (PST) Received: from lmecxl1178.lme.st.com ([80.215.43.103]) by smtp.gmail.com with ESMTPSA id m18-20020adfe952000000b00286ad197346sm1599336wrn.70.2023.01.24.02.56.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 02:56:52 -0800 (PST) From: Etienne Carriere To: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Etienne Carriere , devicetree@vger.kernel.org, Jens Wiklander , Krzysztof Kozlowski , Marc Zyngier , Rob Herring , Sumit Garg , Pascal Paillet Subject: [PATCH v2 1/3] dt-bindings: arm: optee: add interrupt controller properties Date: Tue, 24 Jan 2023 11:56:41 +0100 Message-Id: <20230124105643.1737250-1-etienne.carriere@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230124_025654_804105_C332FDE8 X-CRM114-Status: GOOD ( 14.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adds an optional interrupt controller property to optee firmware node in the DT bindings. Optee driver may embeds an irqchip exposing interrupts notified by the TEE world. Optee registers up to 1 interrupt controller and identifies each line with a line number from 0 to UINT16_MAX. In the example, the platform SCMI device uses optee interrupt irq 5 as async signal to trigger processing of an async incoming SCMI message, in the scope of a CPU DVFS control. A platform can have several SCMI channels driven this way. Optee irqs also permits small embedded devices to share e.g. a gpio expander, a group of wakeup sources, etc... between OP-TEE world (for sensitive services) and Linux world (for non-sensitive services). The physical controller is driven from the TEE which exposes some controls to Linux kernel. Cc: Jens Wiklander Cc: Krzysztof Kozlowski Cc: Marc Zyngier Cc: Rob Herring Cc: Sumit Garg Co-developed-by: Pascal Paillet Signed-off-by: Pascal Paillet Signed-off-by: Etienne Carriere --- Changes since v1: - Added a description to #interrupt-cells property. - Changed of example. Linux wakeup event was subject to discussion and i don't know much about input events in Linux. So move to SCMI. In the example, an SCMI server in OP-TEE world raises optee irq 5 so that Linux scmi optee channel &scmi_cpu_dvfs pushed in the incoming SCMI message in the scmi device for liekly later processing in threaded context. The example includes all parties: optee, scmi, sram, gic. - Obviously rephrased the commit message. - Added Cc: tags --- .../arm/firmware/linaro,optee-tz.yaml | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml b/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml index d4dc0749f9fd..9c00c27f8b2c 100644 --- a/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml +++ b/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml @@ -40,6 +40,14 @@ properties: HVC #0, register assignments register assignments are specified in drivers/tee/optee/optee_smc.h + interrupt-controller: true + + "#interrupt-cells": + const: 1 + description: | + OP-TEE exposes irq for irp chip controllers from OP-TEE world. Each + irq is assigned a single line number identifier used as first argument. + required: - compatible - method @@ -64,3 +72,62 @@ examples: method = "hvc"; }; }; + + - | + #include + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + + scmi { + compatible = "linaro,scmi-optee"; + linaro,optee-channel-id = <0>; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_cpu_dvfs: protocol@13 { + reg = <0x13>; + linaro,optee-channel-id = <1>; + shmem = <&scmi_shm_tx>, <&scmi_shm_rx>; + interrupts-extended = <&optee 5>; + interrupt-names = "a2p"; + #clock-cells = <1>; + }; + }; + }; + + gic: interrupt-controller@a0021000 { + compatible = "arm,cortex-a7-gic"; + reg = <0xa0021000 0x1000>, <0xa0022000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + + sram@2ffff000 { + compatible = "mmio-sram"; + reg = <0x2ffff000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2ffff000 0x1000>; + + scmi_shm_tx: scmi-sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0 0x80>; + }; + + scmi_shm_rx: scmi-sram@100 { + compatible = "arm,scmi-shmem"; + reg = <0x100 0x80>; + }; + }; + };