From patchwork Wed Jan 25 15:10:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sasha Finkelstein X-Patchwork-Id: 13115781 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 33EDCC54E94 for ; Wed, 25 Jan 2023 15:13:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=y/qj0scMHCv48fjTDarsZ0v9o9fETVmJwRObs5B6l6A=; b=xgqQTM1TC+aAcp 1YrTyFYVVdj7GssPIP5yUrg87G3uWDO926PfHCqefINtm9yj2snGWAW6tWTZVgDLJCQS4nHz1MhX+ B3ZOt4yzV6BsIFH/0+NXUqlkizYxcBiF4wtXHVXiWA/AwHHUrhNLbBm+Qi3VN6vFdPn64/cpABYBl 3nq/+aGtK19Mggg9mnH+CXtu9FK84DedaHMvntKlnNCOwUS7RDN9kNtvTjB5rMVJJ5ZFfAMI2jAi8 tyIEFm4CfonBJJfwkMnWR5l+BqgO3SQPukHdzW1UCuyLi9DFVuDCjDt5GAQyZPemxKMINw8YPolO3 EZBo/XZ3uekcydlAnulw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pKhS3-007ket-9s; Wed, 25 Jan 2023 15:12:39 +0000 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pKhQb-007k4j-Fi for linux-arm-kernel@lists.infradead.org; Wed, 25 Jan 2023 15:11:11 +0000 Received: by mail-wr1-x434.google.com with SMTP id n7so17359181wrx.5 for ; Wed, 25 Jan 2023 07:11:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9QdtFduAUazoRi+gFa6YJzP5gQ4JWm55xKraka6mCaE=; b=lXbGlhq05uJS0Pyf8RfesexY78MgfQw+69VaRAoGa4nEy8L+Y4SUx1b55gVjEC6G5L +4dml6/S25KghUBYj7cMpgir6NK+U+lJvLGZbXN809PWdp5jcOx63Xb+3YGerofmtXo+ c9NTE67Z896DDSmoM9iD/gAnDh2kpm2veFmUG1P7km1MjImMhd7GYKd5QB+IuFirGD9g XYtqrk3OhmHmMygk/1KcH7Qh3S2q+Wum2k4Z3ABicmdVHqaUazxUMpfAd30ViU8zLPvU 62uMpnEePNpM7l1w4dlAkHXENn4dKjUJs1hA+qfNLs0eQ7mZ5/bVwiR+qGs0sA60pVvJ METg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9QdtFduAUazoRi+gFa6YJzP5gQ4JWm55xKraka6mCaE=; b=C9Szsv3E2giAgvBfQM850JtCdIJK0vRZkP708RAqpmBdztwYXrN5JnloLpzxkAvQ1l Wit8hlfZ6G7KvCfMMWF78vxszML7tZOEk6ovQvPGbtYzDchS4JdG1cglAbYNb6LiBDa8 EIPtyVthL/bTiuEqI8HUQqBW8Wp9eGRnxPsOMjmZPvY3sXvDsTKGbAZZOf0Xexk+VMzU mh6ddxQwJp7/tEdqXOchOfb2ULKVIT6tNQugddR2aGI2Ijkn4Rajr2l3tzBwUtiBSvW6 jgY341tkJuNKyO9wheqgM+l5hNSPCrhirEMl7NTWA5EgsB40h1aLW3MslaM1ziUQ8tpq c5ag== X-Gm-Message-State: AO0yUKXtE3Cpjz5C8H94d5SfwHzANnCo2Q+JpskSZTDAzZ51pvh5bkPr j35v7Hs3lY6S0UwEhUVW7Dc= X-Google-Smtp-Source: AK7set/wtbF3+5CCefTbcW6nAY8InllI2YFh1DVZbqqQkvI4VGT9t6jAS5+ZerrcllKE4BSArSFDnw== X-Received: by 2002:a5d:6e05:0:b0:2bf:b92b:8a8a with SMTP id h5-20020a5d6e05000000b002bfb92b8a8amr2340757wrz.7.1674659467800; Wed, 25 Jan 2023 07:11:07 -0800 (PST) Received: from localhost ([82.222.96.52]) by smtp.gmail.com with UTF8SMTPSA id l14-20020a5d410e000000b002bdd8f12effsm4534513wrp.30.2023.01.25.07.11.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 25 Jan 2023 07:11:06 -0800 (PST) From: Sasha Finkelstein To: u.kleine-koenig@pengutronix.de, thierry.reding@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sasha Finkelstein Subject: [PATCH v7 2/5] pwm: Add Apple PWM controller Date: Wed, 25 Jan 2023 18:10:38 +0300 Message-Id: <20230125151041.55483-3-fnkl.kernel@gmail.com> X-Mailer: git-send-email 2.37.1 (Apple Git-137.1) In-Reply-To: <20230125151041.55483-1-fnkl.kernel@gmail.com> References: <20230125151041.55483-1-fnkl.kernel@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230125_071109_565765_33213092 X-CRM114-Status: GOOD ( 28.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adds the Apple PWM controller driver. Signed-off-by: Sasha Finkelstein Acked-by: Sven Peter --- drivers/pwm/Kconfig | 12 +++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-apple.c | 159 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 172 insertions(+) create mode 100644 drivers/pwm/pwm-apple.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index dae023d783a2..8df861b1f4a3 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -51,6 +51,18 @@ config PWM_AB8500 To compile this driver as a module, choose M here: the module will be called pwm-ab8500. +config PWM_APPLE + tristate "Apple SoC PWM support" + depends on ARCH_APPLE || COMPILE_TEST + help + Generic PWM framework driver for PWM controller present on + Apple SoCs + + Say Y here if you have an ARM Apple laptop, otherwise say N + + To compile this driver as a module, choose M here: the module + will be called pwm-apple. + config PWM_ATMEL tristate "Atmel PWM support" depends on ARCH_AT91 || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 7bf1a29f02b8..19899b912e00 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_PWM) += core.o obj-$(CONFIG_PWM_SYSFS) += sysfs.o obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o +obj-$(CONFIG_PWM_APPLE) += pwm-apple.o obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o diff --git a/drivers/pwm/pwm-apple.c b/drivers/pwm/pwm-apple.c new file mode 100644 index 000000000000..551e07d49bf7 --- /dev/null +++ b/drivers/pwm/pwm-apple.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Driver for the Apple SoC PWM controller + * + * Copyright The Asahi Linux Contributors + * + * Limitations: + * - The writes to cycle registers are shadowed until a write to + * the control register. + * - If both OFF_CYCLES and ON_CYCLES are set to 0, the output + * is a constant off signal. + * - When APPLE_PWM_CTRL is set to 0, the output is constant low + */ + +#include +#include +#include +#include +#include +#include + +#define APPLE_PWM_CTRL 0x00 +#define APPLE_PWM_ON_CYCLES 0x1c +#define APPLE_PWM_OFF_CYCLES 0x18 + +#define APPLE_PWM_CTRL_ENABLE BIT(0) +#define APPLE_PWM_CTRL_MODE BIT(2) +#define APPLE_PWM_CTRL_UPDATE BIT(5) +#define APPLE_PWM_CTRL_TRIGGER BIT(9) +#define APPLE_PWM_CTRL_INVERT BIT(10) +#define APPLE_PWM_CTRL_OUTPUT_ENABLE BIT(14) + +struct apple_pwm { + struct pwm_chip chip; + void __iomem *base; + u64 clkrate; +}; + +static inline struct apple_pwm *to_apple_pwm(struct pwm_chip *chip) +{ + return container_of(chip, struct apple_pwm, chip); +} + +static int apple_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct apple_pwm *fpwm; + + if (state->polarity == PWM_POLARITY_INVERSED) + return -EINVAL; + + fpwm = to_apple_pwm(chip); + if (state->enabled) { + u64 on_cycles, off_cycles; + + on_cycles = mul_u64_u64_div_u64(fpwm->clkrate, + state->duty_cycle, NSEC_PER_SEC); + if (on_cycles > 0xFFFFFFFF) + return -ERANGE; + + off_cycles = mul_u64_u64_div_u64(fpwm->clkrate, + state->period, NSEC_PER_SEC) - on_cycles; + if (off_cycles > 0xFFFFFFFF) + return -ERANGE; + + writel(on_cycles, fpwm->base + APPLE_PWM_ON_CYCLES); + writel(off_cycles, fpwm->base + APPLE_PWM_OFF_CYCLES); + writel(APPLE_PWM_CTRL_ENABLE | APPLE_PWM_CTRL_OUTPUT_ENABLE | APPLE_PWM_CTRL_UPDATE, + fpwm->base + APPLE_PWM_CTRL); + } else { + writel(0, fpwm->base + APPLE_PWM_CTRL); + } + return 0; +} + +static int apple_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct apple_pwm *fpwm; + u32 on_cycles, off_cycles, ctrl; + + fpwm = to_apple_pwm(chip); + + ctrl = readl(fpwm->base + APPLE_PWM_CTRL); + on_cycles = readl(fpwm->base + APPLE_PWM_ON_CYCLES); + off_cycles = readl(fpwm->base + APPLE_PWM_OFF_CYCLES); + + state->enabled = (ctrl & APPLE_PWM_CTRL_ENABLE) && (ctrl & APPLE_PWM_CTRL_OUTPUT_ENABLE); + state->polarity = PWM_POLARITY_NORMAL; + // on_cycles + off_cycles is 33 bits, NSEC_PER_SEC is 30, there is no overflow + state->duty_cycle = DIV64_U64_ROUND_UP((u64)on_cycles * NSEC_PER_SEC, fpwm->clkrate); + state->period = DIV64_U64_ROUND_UP(((u64)off_cycles + (u64)on_cycles) * + NSEC_PER_SEC, fpwm->clkrate); + + return 0; +} + +static const struct pwm_ops apple_pwm_ops = { + .apply = apple_pwm_apply, + .get_state = apple_pwm_get_state, + .owner = THIS_MODULE, +}; + +static int apple_pwm_probe(struct platform_device *pdev) +{ + struct apple_pwm *fpwm; + struct clk *clk; + int ret; + + fpwm = devm_kzalloc(&pdev->dev, sizeof(*fpwm), GFP_KERNEL); + if (!fpwm) + return -ENOMEM; + + fpwm->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(fpwm->base)) + return PTR_ERR(fpwm->base); + + clk = devm_clk_get_enabled(&pdev->dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(clk), "unable to get the clock"); + + /* + * Uses the 24MHz system clock on all existing devices, can only + * happen if the device tree is broken + * + * This check is done to prevent an overflow in .apply + */ + fpwm->clkrate = clk_get_rate(clk); + if (fpwm->clkrate > NSEC_PER_SEC) + return dev_err_probe(&pdev->dev, -EINVAL, "pwm clock out of range"); + + fpwm->chip.dev = &pdev->dev; + fpwm->chip.npwm = 1; + fpwm->chip.ops = &apple_pwm_ops; + + ret = devm_pwmchip_add(&pdev->dev, &fpwm->chip); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "unable to add pwm chip"); + + return 0; +} + +static const struct of_device_id apple_pwm_of_match[] = { + { .compatible = "apple,s5l-fpwm" }, + {} +}; +MODULE_DEVICE_TABLE(of, apple_pwm_of_match); + +static struct platform_driver apple_pwm_driver = { + .probe = apple_pwm_probe, + .driver = { + .name = "apple-pwm", + .of_match_table = apple_pwm_of_match, + }, +}; +module_platform_driver(apple_pwm_driver); + +MODULE_DESCRIPTION("Apple SoC PWM driver"); +MODULE_LICENSE("Dual MIT/GPL");