| Message ID | 20230202-asahi-t8112-dt-v1-6-cb5442d1c229@jannau.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Device trees for Apple M2 (t8112) based devices | expand |
On 12/02/2023 16:41, Janne Grunau wrote: > The PMUs on the avalanche and blizzard CPU two micro-architectures are > mostly compatible with M1 ones. They miss support for a single counter > according to Apple's PMU counter list. > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml index dbb6f3dc5ae5..e14358bf0b9c 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -20,6 +20,8 @@ properties: items: - enum: - apm,potenza-pmu + - apple,avalanche-pmu + - apple,blizzard-pmu - apple,firestorm-pmu - apple,icestorm-pmu - arm,armv8-pmuv3 # Only for s/w models
The PMUs on the avalanche and blizzard CPU two micro-architectures are mostly compatible with M1 ones. They miss support for a single counter according to Apple's PMU counter list. Signed-off-by: Janne Grunau <j@jannau.net> --- This trivial dt-bindings update should be merged through the asahi-soc tree to ensure validation of the Apple M2 (t8112) devicetrees in this series. The necessary driver update will be sent separately. --- Documentation/devicetree/bindings/arm/pmu.yaml | 2 ++ 1 file changed, 2 insertions(+)