From patchwork Fri Feb 3 04:20:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 13127000 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 510BEC636CC for ; Fri, 3 Feb 2023 04:26:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=Nc7nq1lzW4FGU6I8PqhamPrs8MDFlLJu3hJNWKClw9k=; b=Jea6a1ZpzapbrfOk1lTbFi0bRF SL2xcgduiGcO6gCabaa5DAIBnm3X1J3IpZxZ0VnL/iaCX2IgndilCBUuf8Lz+5l4ufAjsIAVDiQqC EHIWzBs1B/J6wVq3DqgU9dMNX3kfJT2SV/IQfvEcmXQUF98dxWYKphTEkdsl7KYEX1yoTS2ZkzX7U 3QTjCv1W3DfCHsTfZsSiT1MDUSba9dIzrrcnN/F6T6syVTHibJuyCul4pT2EXy7vZZsHFY+RSu3/g TySG9xxCXgfsrkKhe++Kj6wWg7302CjnZdTwyyxjK3mByjEnvoqyZ1aWwSUk9BsIWlUSPMOKQVaRD GoKiXzCw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pNne3-000KiP-J9; Fri, 03 Feb 2023 04:25:52 +0000 Received: from mail-yb1-xb4a.google.com ([2607:f8b0:4864:20::b4a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pNnby-000Jc4-0E for linux-arm-kernel@lists.infradead.org; Fri, 03 Feb 2023 04:23:44 +0000 Received: by mail-yb1-xb4a.google.com with SMTP id b18-20020a253412000000b0085747dc8317so3749275yba.15 for ; Thu, 02 Feb 2023 20:23:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=rjHuOROaPh04hBIryzlS3UOwUzWVXjEKlopD+fhxM6Q=; b=ZwkdcLbW28CGT5q2oMQ7rph4wKqhu4THcTXKCGfhgxf1olfxceL475/g9ILy30bq7X Yt2shk2Z3/55BWhYiUqR8iJl6EysMSZEwq4WZzCZMZWy2orA2HMxpsbZIg/o3bh8ZqfW 5DROz9ICqHUHCb/bfiExo5XUkTHjkqCq9SqHMLxMoNGjfi8jC3Rdd6HNTdVswsRkJeHG ZotPLrCH4uX0eKstAc2GRJyeQjE/igLlQbBpVBqklScwk6e9vuBHBwyUj7k9PMo4SFua q30MOaQFuh+kKToOgv38mrEZ4Uo0uxfyNEKnY2lUcaTjXqY0kWWnPySfOEdCafW22npv iEbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=rjHuOROaPh04hBIryzlS3UOwUzWVXjEKlopD+fhxM6Q=; b=a4D4BqyLiUtXUJpKjrP0NQBAEh3tRY+Y8EX6Crizyh3I2diQI4iDl70rvwV58ACbMI c5ueIs+MHrkHsbONUfmnwCs3+6nCr8vQeFLjECLdFdFnoA/HkCvivjX5L5zDnraB7cYs XM0MYOCRJA4Hiw2MVbl2zDMwk4sEs1zDyuwwjttmtK5yKSBjoHno/Zw4BNpJy+xnlsIU gejDP5UTEX9cS8O77B8Ovg2/YzCTExGFXi5QyBdLiEuX7nD96uPMdftXMemMOeHFnQ5j hFyQaLROm2I0I0zaxUHQM8Xx4F9id3AHpQH9bCoucdIOg3Nwgu0fNiSownFFHflxf4Q/ 6+dw== X-Gm-Message-State: AO0yUKXwqAHgduqNSDh7oXMAeV0geHXu/yi1imo9Awn3RaPjYfl8Ysmt MLPoLreagHckgvsHctMFJbY0yLSJ0e4= X-Google-Smtp-Source: AK7set/rNgLZtJ+6USHfQmvNtMEkp1YLxm5xnM8Ib/JZT7xCM+iM+JYo+d/C8Pil6f6TG+WD4DTI5r/fK3E= X-Received: from reijiw-west4.c.googlers.com ([fda3:e722:ac3:cc00:20:ed76:c0a8:aa1]) (user=reijiw job=sendgmr) by 2002:a81:d10c:0:b0:507:b797:f1b with SMTP id w12-20020a81d10c000000b00507b7970f1bmr905069ywi.468.1675398212958; Thu, 02 Feb 2023 20:23:32 -0800 (PST) Date: Thu, 2 Feb 2023 20:20:52 -0800 In-Reply-To: <20230203042056.1794649-1-reijiw@google.com> Mime-Version: 1.0 References: <20230203042056.1794649-1-reijiw@google.com> X-Mailer: git-send-email 2.39.1.519.gcb327c4b5f-goog Message-ID: <20230203042056.1794649-9-reijiw@google.com> Subject: [PATCH v3 10/14] KVM: arm64: PMU: Allow userspace to limit PMCR_EL0.N for the guest From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.linux.dev Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Paolo Bonzini , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Shaoqin Huang , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230202_202342_081995_F0BC28F5 X-CRM114-Status: GOOD ( 24.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org KVM does not yet support userspace modifying PMCR_EL0.N (With the previous patch, KVM ignores what is written by upserspace). Add support userspace limiting PMCR_EL0.N. Disallow userspace to set PMCR_EL0.N to a value that is greater than the host value (KVM_SET_ONE_REG will fail), as KVM doesn't support more event counters than the host HW implements. Although this is an ABI change, this change only affects userspace setting PMCR_EL0.N to a larger value than the host. As accesses to unadvertised event counters indices is CONSTRAINED UNPREDICTABLE behavior, and PMCR_EL0.N was reset to the host value on every vCPU reset before this series, I can't think of any use case where a user space would do that. Also, ignore writes to read-only bits that are cleared on vCPU reset, and RES{0,1} bits (including writable bits that KVM doesn't support yet), as those bits shouldn't be modified (at least with the current KVM). Signed-off-by: Reiji Watanabe --- arch/arm64/include/asm/kvm_host.h | 3 ++ arch/arm64/kvm/pmu-emul.c | 1 + arch/arm64/kvm/sys_regs.c | 48 ++++++++++++++++++++++++++++++- 3 files changed, 51 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 734f1b6f7468..cd0014d1ec16 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -236,6 +236,9 @@ struct kvm_arch { /* PMCR_EL0.N value for the guest */ u8 pmcr_n; + /* Limit value of PMCR_EL0.N for the guest */ + u8 pmcr_n_limit; + /* Hypercall features firmware registers' descriptor */ struct kvm_smccc_features smccc_feat; diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 3053c06db7a9..ff4ec678afbd 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -890,6 +890,7 @@ int kvm_arm_set_vm_pmu(struct kvm *kvm, struct arm_pmu *arm_pmu) * while the latter does not. */ kvm->arch.pmcr_n = arm_pmu->num_events - 1; + kvm->arch.pmcr_n_limit = arm_pmu->num_events - 1; return 0; } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index aba93db29697..959bd142b797 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -949,6 +949,52 @@ static int get_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, return 0; } +static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, + u64 val) +{ + struct kvm *kvm = vcpu->kvm; + u64 new_n, mutable_mask; + int ret = 0; + + new_n = FIELD_GET(ARMV8_PMU_PMCR_N, val); + + if (unlikely(new_n != kvm->arch.pmcr_n)) { + mutex_lock(&kvm->lock); + /* + * The vCPU can't have more counters than the PMU + * hardware implements. + */ + if (new_n <= kvm->arch.pmcr_n_limit) + kvm->arch.pmcr_n = new_n; + else + ret = -EINVAL; + + mutex_unlock(&kvm->lock); + if (ret) + return ret; + } + + /* + * Ignore writes to RES0 bits, read only bits that are cleared on + * vCPU reset, and writable bits that KVM doesn't support yet. + * (i.e. only PMCR.N and bits [7:0] are mutable from userspace) + * The LP bit is RES0 when FEAT_PMUv3p5 is not supported on the vCPU. + * But, we leave the bit as it is here, as the vCPU's PMUver might + * be changed later (NOTE: the bit will be cleared on first vCPU run + * if necessary). + */ + mutable_mask = (ARMV8_PMU_PMCR_MASK | ARMV8_PMU_PMCR_N); + val &= mutable_mask; + val |= (__vcpu_sys_reg(vcpu, r->reg) & ~mutable_mask); + + /* The LC bit is RES1 when AArch32 is not supported */ + if (!kvm_supports_32bit_el0()) + val |= ARMV8_PMU_PMCR_LC; + + __vcpu_sys_reg(vcpu, r->reg) = val; + return 0; +} + /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ @@ -1723,7 +1769,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_SVCR), undef_access }, { PMU_SYS_REG(SYS_PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, - .reg = PMCR_EL0, .get_user = get_pmcr }, + .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr }, { PMU_SYS_REG(SYS_PMCNTENSET_EL0), .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, { PMU_SYS_REG(SYS_PMCNTENCLR_EL0),