| Message ID | 20230209151632.275883-7-clement.leger@bootlin.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | net: stmmac: add renesas,rzn1-gmac support | expand |
Hi Clément, On Thu, Feb 9, 2023 at 4:14 PM Clément Léger <clement.leger@bootlin.com> wrote: > RZ/N1 SoC includes two MAC named GMACx that are compatible with the > "snps,dwmac" driver. GMAC1 is connected directly to the MII converter > port 1. Since this MII converter is represented using a PCS driver, it > uses the renesas specific compatible driver which uses this PCS. > > Signed-off-by: Clément Léger <clement.leger@bootlin.com> Thanks for your patch! > --- a/arch/arm/boot/dts/r9a06g032.dtsi > +++ b/arch/arm/boot/dts/r9a06g032.dtsi > @@ -304,6 +304,24 @@ dma1: dma-controller@40105000 { > data-width = <8>; > }; > > + gmac1: ethernet@44000000 { > + compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; > + reg = <0x44000000 0x2000>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; > + clock-names = "stmmaceth"; Please move clock-names below clocks, like in all other nodes. > + clocks = <&sysctrl R9A06G032_HCLK_GMAC0>; Missing power-domains property. > + snps,multicast-filter-bins = <256>; > + snps,perfect-filter-entries = <128>; > + tx-fifo-depth = <2048>; > + rx-fifo-depth = <4096>; > + pcs-handle = <&mii_conv1>; > + status = "disabled"; > + }; > + > gmac2: ethernet@44002000 { > compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; > reg = <0x44002000 0x2000>; Gr{oetje,eeting}s, Geert
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 41e19c0986ce..ba32e4429b01 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -304,6 +304,24 @@ dma1: dma-controller@40105000 { data-width = <8>; }; + gmac1: ethernet@44000000 { + compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; + reg = <0x44000000 0x2000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + clock-names = "stmmaceth"; + clocks = <&sysctrl R9A06G032_HCLK_GMAC0>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <2048>; + rx-fifo-depth = <4096>; + pcs-handle = <&mii_conv1>; + status = "disabled"; + }; + gmac2: ethernet@44002000 { compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; reg = <0x44002000 0x2000>;
RZ/N1 SoC includes two MAC named GMACx that are compatible with the "snps,dwmac" driver. GMAC1 is connected directly to the MII converter port 1. Since this MII converter is represented using a PCS driver, it uses the renesas specific compatible driver which uses this PCS. Signed-off-by: Clément Léger <clement.leger@bootlin.com> --- arch/arm/boot/dts/r9a06g032.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)