| Message ID | 20230217145645.1768659-6-herve.codina@bootlin.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add the PowerQUICC audio support using the QMC | expand |
Le 17/02/2023 à 15:56, Herve Codina a écrit : > Add support for the QMC (QUICC Multichannel Controller) > available in some PowerQUICC SoC such as MPC885 or MPC866. > > Signed-off-by: Herve Codina <herve.codina@bootlin.com> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> > --- > .../soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml | 172 ++++++++++++++++++ > 1 file changed, 172 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml > > diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml > new file mode 100644 > index 000000000000..4ebbc7d52981 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml > @@ -0,0 +1,172 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: PowerQUICC CPM QUICC Multichannel Controller (QMC) > + > +maintainers: > + - Herve Codina <herve.codina@bootlin.com> > + > +description: > + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within one > + serial controller using the same TDM physical interface routed from TSA. > + > +properties: > + compatible: > + items: > + - enum: > + - fsl,mpc885-scc-qmc > + - fsl,mpc866-scc-qmc > + - const: fsl,cpm1-scc-qmc > + > + reg: > + items: > + - description: SCC (Serial communication controller) register base > + - description: SCC parameter ram base > + - description: Dual port ram base > + > + reg-names: > + items: > + - const: scc_regs > + - const: scc_pram > + - const: dpram > + > + interrupts: > + maxItems: 1 > + description: SCC interrupt line in the CPM interrupt controller > + > + fsl,tsa-serial: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + - items: > + - description: phandle to TSA node > + - enum: [1, 2, 3] > + description: | > + TSA serial interface (dt-bindings/soc/cpm1-fsl,tsa.h defines these > + values) > + - 1: SCC2 > + - 2: SCC3 > + - 3: SCC4 > + description: > + Should be a phandle/number pair. The phandle to TSA node and the TSA > + serial interface to use. > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > + '#fsl,chan-cells': > + $ref: /schemas/types.yaml#/definitions/uint32 > + const: 1 > + description: > + QMC consumers that use a phandle to QMC need to pass the channel number > + with this phandle. > + For instance "fsl,qmc-chan = <&qmc 16>;". > + > +patternProperties: > + '^channel@([0-9]|[1-5][0-9]|6[0-3])$': > + description: > + A channel managed by this controller > + type: object > + > + properties: > + reg: > + minimum: 0 > + maximum: 63 > + description: > + The channel number > + > + fsl,operational-mode: > + $ref: /schemas/types.yaml#/definitions/string > + enum: [transparent, hdlc] > + default: transparent > + description: | > + The channel operational mode > + - hdlc: The channel handles HDLC frames > + - transparent: The channel handles raw data without any processing > + > + fsl,reverse-data: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + The bit order as seen on the channels is reversed, > + transmitting/receiving the MSB of each octet first. > + This flag is used only in 'transparent' mode. > + > + fsl,tx-ts-mask: > + $ref: /schemas/types.yaml#/definitions/uint64 > + description: > + Channel assigned Tx time-slots within the Tx time-slots routed by the > + TSA to this cell. > + > + fsl,rx-ts-mask: > + $ref: /schemas/types.yaml#/definitions/uint64 > + description: > + Channel assigned Rx time-slots within the Rx time-slots routed by the > + TSA to this cell. > + > + required: > + - reg > + - fsl,tx-ts-mask > + - fsl,rx-ts-mask > + > +required: > + - compatible > + - reg > + - reg-names > + - interrupts > + - fsl,tsa-serial > + - '#address-cells' > + - '#size-cells' > + - '#fsl,chan-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/soc/cpm1-fsl,tsa.h> > + > + qmc@a60 { > + compatible = "fsl,mpc885-scc-qmc", "fsl,cpm1-scc-qmc"; > + reg = <0xa60 0x20>, > + <0x3f00 0xc0>, > + <0x2000 0x1000>; > + reg-names = "scc_regs", "scc_pram", "dpram"; > + interrupts = <27>; > + interrupt-parent = <&CPM_PIC>; > + > + #address-cells = <1>; > + #size-cells = <0>; > + #fsl,chan-cells = <1>; > + > + fsl,tsa-serial = <&tsa FSL_CPM_TSA_SCC4>; > + > + channel@16 { > + /* Ch16 : First 4 even TS from all routed from TSA */ > + reg = <16>; > + fsl,mode = "transparent"; > + fsl,reverse-data; > + fsl,tx-ts-mask = <0x00000000 0x000000aa>; > + fsl,rx-ts-mask = <0x00000000 0x000000aa>; > + }; > + > + channel@17 { > + /* Ch17 : First 4 odd TS from all routed from TSA */ > + reg = <17>; > + fsl,mode = "transparent"; > + fsl,reverse-data; > + fsl,tx-ts-mask = <0x00000000 0x00000055>; > + fsl,rx-ts-mask = <0x00000000 0x00000055>; > + }; > + > + channel@19 { > + /* Ch19 : 8 TS (TS 8..15) from all routed from TSA */ > + reg = <19>; > + fsl,mode = "hdlc"; > + fsl,tx-ts-mask = <0x00000000 0x0000ff00>; > + fsl,rx-ts-mask = <0x00000000 0x0000ff00>; > + }; > + };
diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml new file mode 100644 index 000000000000..4ebbc7d52981 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PowerQUICC CPM QUICC Multichannel Controller (QMC) + +maintainers: + - Herve Codina <herve.codina@bootlin.com> + +description: + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within one + serial controller using the same TDM physical interface routed from TSA. + +properties: + compatible: + items: + - enum: + - fsl,mpc885-scc-qmc + - fsl,mpc866-scc-qmc + - const: fsl,cpm1-scc-qmc + + reg: + items: + - description: SCC (Serial communication controller) register base + - description: SCC parameter ram base + - description: Dual port ram base + + reg-names: + items: + - const: scc_regs + - const: scc_pram + - const: dpram + + interrupts: + maxItems: 1 + description: SCC interrupt line in the CPM interrupt controller + + fsl,tsa-serial: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to TSA node + - enum: [1, 2, 3] + description: | + TSA serial interface (dt-bindings/soc/cpm1-fsl,tsa.h defines these + values) + - 1: SCC2 + - 2: SCC3 + - 3: SCC4 + description: + Should be a phandle/number pair. The phandle to TSA node and the TSA + serial interface to use. + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#fsl,chan-cells': + $ref: /schemas/types.yaml#/definitions/uint32 + const: 1 + description: + QMC consumers that use a phandle to QMC need to pass the channel number + with this phandle. + For instance "fsl,qmc-chan = <&qmc 16>;". + +patternProperties: + '^channel@([0-9]|[1-5][0-9]|6[0-3])$': + description: + A channel managed by this controller + type: object + + properties: + reg: + minimum: 0 + maximum: 63 + description: + The channel number + + fsl,operational-mode: + $ref: /schemas/types.yaml#/definitions/string + enum: [transparent, hdlc] + default: transparent + description: | + The channel operational mode + - hdlc: The channel handles HDLC frames + - transparent: The channel handles raw data without any processing + + fsl,reverse-data: + $ref: /schemas/types.yaml#/definitions/flag + description: + The bit order as seen on the channels is reversed, + transmitting/receiving the MSB of each octet first. + This flag is used only in 'transparent' mode. + + fsl,tx-ts-mask: + $ref: /schemas/types.yaml#/definitions/uint64 + description: + Channel assigned Tx time-slots within the Tx time-slots routed by the + TSA to this cell. + + fsl,rx-ts-mask: + $ref: /schemas/types.yaml#/definitions/uint64 + description: + Channel assigned Rx time-slots within the Rx time-slots routed by the + TSA to this cell. + + required: + - reg + - fsl,tx-ts-mask + - fsl,rx-ts-mask + +required: + - compatible + - reg + - reg-names + - interrupts + - fsl,tsa-serial + - '#address-cells' + - '#size-cells' + - '#fsl,chan-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/soc/cpm1-fsl,tsa.h> + + qmc@a60 { + compatible = "fsl,mpc885-scc-qmc", "fsl,cpm1-scc-qmc"; + reg = <0xa60 0x20>, + <0x3f00 0xc0>, + <0x2000 0x1000>; + reg-names = "scc_regs", "scc_pram", "dpram"; + interrupts = <27>; + interrupt-parent = <&CPM_PIC>; + + #address-cells = <1>; + #size-cells = <0>; + #fsl,chan-cells = <1>; + + fsl,tsa-serial = <&tsa FSL_CPM_TSA_SCC4>; + + channel@16 { + /* Ch16 : First 4 even TS from all routed from TSA */ + reg = <16>; + fsl,mode = "transparent"; + fsl,reverse-data; + fsl,tx-ts-mask = <0x00000000 0x000000aa>; + fsl,rx-ts-mask = <0x00000000 0x000000aa>; + }; + + channel@17 { + /* Ch17 : First 4 odd TS from all routed from TSA */ + reg = <17>; + fsl,mode = "transparent"; + fsl,reverse-data; + fsl,tx-ts-mask = <0x00000000 0x00000055>; + fsl,rx-ts-mask = <0x00000000 0x00000055>; + }; + + channel@19 { + /* Ch19 : 8 TS (TS 8..15) from all routed from TSA */ + reg = <19>; + fsl,mode = "hdlc"; + fsl,tx-ts-mask = <0x00000000 0x0000ff00>; + fsl,rx-ts-mask = <0x00000000 0x0000ff00>; + }; + };