diff mbox series

[v10,3/9] arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node

Message ID 20230221120612.27366-4-r-gunasekaran@ti.com (mailing list archive)
State New, archived
Headers show
Series arm64: j721s2: Add support for additional IPs | expand

Commit Message

Ravi Gunasekaran Feb. 21, 2023, 12:06 p.m. UTC 
From: Matt Ranostay <mranostay@ti.com>

Add dt node for the single instance of WIZ (SERDES wrapper) and
SERDES module shared by PCIe, eDP and USB.

Signed-off-by: Matt Ranostay <mranostay@ti.com>
Link: https://lore.kernel.org/r/20221122101616.770050-3-mranostay@ti.com
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
---
I had reviewed this patch in the v7 series [1].
Since I'm taking over upstreaming this series, I removed the self
Reviewed-by tag.

Links:

[1] - https://lore.kernel.org/lkml/4173e0c6-61d9-5b79-44ec-317870de070b@ti.com/

 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 60 +++++++++++++++++++++-
 1 file changed, 59 insertions(+), 1 deletion(-)

Comments

Nishanth Menon Feb. 21, 2023, 2:01 p.m. UTC | #1 
On 17:36-20230221, Ravi Gunasekaran wrote:
> From: Matt Ranostay <mranostay@ti.com>
> 
> Add dt node for the single instance of WIZ (SERDES wrapper) and
> SERDES module shared by PCIe, eDP and USB.

[...]

> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index 84e5689fff9f..af6c93f0a055 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
[...]
> @@ -33,11 +44,18 @@
>  		#size-cells = <1>;
>  		ranges = <0x00 0x00 0x00104000 0x18000>;
>  
> -		usb_serdes_mux: mux-controller@0 {
> +		usb_serdes_mux: mux-controller-0 {

was'nt this just introduced in the patch just prior, if so, NAK,
do the changes where they are introduced.

>  			compatible = "mmio-mux";
>  			#mux-control-cells = <1>;
>  			mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
>  		};
Ravi Gunasekaran Feb. 22, 2023, 4:53 a.m. UTC | #2 
On 21/02/23 7:31 pm, Nishanth Menon wrote:
> On 17:36-20230221, Ravi Gunasekaran wrote:
>> From: Matt Ranostay <mranostay@ti.com>
>>
>> Add dt node for the single instance of WIZ (SERDES wrapper) and
>> SERDES module shared by PCIe, eDP and USB.
> 
> [...]
> 
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>> index 84e5689fff9f..af6c93f0a055 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> [...]
>> @@ -33,11 +44,18 @@
>>  		#size-cells = <1>;
>>  		ranges = <0x00 0x00 0x00104000 0x18000>;
>>  
>> -		usb_serdes_mux: mux-controller@0 {
>> +		usb_serdes_mux: mux-controller-0 {
> 
> was'nt this just introduced in the patch just prior, if so, NAK,
> do the changes where they are introduced.

Noted. I will fix this.
Thanks for reviewing.

> 
>>  			compatible = "mmio-mux";
>>  			#mux-control-cells = <1>;
>>  			mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
>>  		};
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 84e5689fff9f..af6c93f0a055 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -5,6 +5,17 @@ 
  * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
  */
 
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy-ti.h>
+
+/ {
+	serdes_refclk: clock-cmnrefclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+};
+
 &cbass_main {
 	msmc_ram: sram@70000000 {
 		compatible = "mmio-sram";
@@ -33,11 +44,18 @@ 
 		#size-cells = <1>;
 		ranges = <0x00 0x00 0x00104000 0x18000>;
 
-		usb_serdes_mux: mux-controller@0 {
+		usb_serdes_mux: mux-controller-0 {
 			compatible = "mmio-mux";
 			#mux-control-cells = <1>;
 			mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
 		};
+
+		serdes_ln_ctrl: mux-controller-80 {
+			compatible = "mmio-mux";
+			#mux-control-cells = <1>;
+			mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
+					<0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
+		};
 	};
 
 	gic500: interrupt-controller@1800000 {
@@ -791,6 +809,46 @@ 
 		};
 	};
 
+	serdes_wiz0: wiz@5060000 {
+		compatible = "ti,j721s2-wiz-10g";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
+		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+		num-lanes = <4>;
+		#reset-cells = <1>;
+		#clock-cells = <1>;
+		ranges = <0x5060000 0x0 0x5060000 0x10000>;
+
+		assigned-clocks = <&k3_clks 365 3>;
+		assigned-clock-parents = <&k3_clks 365 7>;
+
+		status = "disabled";
+
+		serdes0: serdes@5060000 {
+			compatible = "ti,j721e-serdes-10g";
+			reg = <0x05060000 0x00010000>;
+			reg-names = "torrent_phy";
+			resets = <&serdes_wiz0 0>;
+			reset-names = "torrent_reset";
+			clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+				 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+			clock-names = "refclk", "phy_en_refclk";
+			assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+					  <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+					  <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+			assigned-clock-parents = <&k3_clks 365 3>,
+						 <&k3_clks 365 3>,
+						 <&k3_clks 365 3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#clock-cells = <1>;
+
+			status = "disabled";
+		};
+	};
+
 	main_mcan0: can@2701000 {
 		compatible = "bosch,m_can";
 		reg = <0x00 0x02701000 0x00 0x200>,