| Message ID | 20230306195438.1557851-2-ryan.roberts@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM: arm64: Support FEAT_LPA2 at hyp s1 and vm s2 | expand |
On Mon, Mar 06, 2023 at 07:54:27PM +0000, Ryan Roberts wrote: > FEAT_LPA2 impacts tlb invalidation in 2 ways; Firstly, the TTL field in > the non-range tlbi instructions can now validly take a 0 value for the > 4KB granule (this is due to the extra level of translation). Secondly, > the BADDR field in the range tlbi instructions must be aligned to 64KB > when LPA2 is in use (TCR.DS=1). Changes are required for tlbi to > continue to operate correctly when LPA2 is in use. > > KVM only uses the non-range (__tlbi_level()) routines. Therefore we only > solve the first problem with this patch. There are some patches on the list to add support for range invalidation in KVM: https://lore.kernel.org/r/20230206172340.2639971-1-rananta@google.com > diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h > index 412a3b9a3c25..67dd47df42d5 100644 > --- a/arch/arm64/include/asm/tlbflush.h > +++ b/arch/arm64/include/asm/tlbflush.h > @@ -93,19 +93,22 @@ static inline unsigned long get_trans_granule(void) > * When ARMv8.4-TTL exists, TLBI operations take an additional hint for > * the level at which the invalidation must take place. If the level is > * wrong, no invalidation may take place. In the case where the level > - * cannot be easily determined, a 0 value for the level parameter will > - * perform a non-hinted invalidation. > + * cannot be easily determined, the value TLBI_TTL_UNKNOWN will perform > + * a non-hinted invalidation. Any provided level outside the hint range > + * will also cause fall-back to non-hinted invalidation. > * > * For Stage-2 invalidation, use the level values provided to that effect > * in asm/stage2_pgtable.h. > */ > #define TLBI_TTL_MASK GENMASK_ULL(47, 44) > > +#define TLBI_TTL_UNKNOWN (-1) > + > #define __tlbi_level(op, addr, level) do { \ > u64 arg = addr; \ > \ > if (cpus_have_const_cap(ARM64_HAS_ARMv8_4_TTL) && \ > - level) { \ > + level >= 0 && level <= 3) { \ I'd just use level != TLBI_TTL_UNKNOWN here. > u64 ttl = level & 3; \ > ttl |= get_trans_granule() << 2; \ > arg &= ~TLBI_TTL_MASK; \ > @@ -133,16 +136,17 @@ static inline unsigned long get_trans_granule(void) > * [BADDR, BADDR + (NUM + 1) * 2^(5*SCALE + 1) * PAGESIZE) > * > */ > -#define __TLBI_VADDR_RANGE(addr, asid, scale, num, ttl) \ > - ({ \ > - unsigned long __ta = (addr) >> PAGE_SHIFT; \ > - __ta &= GENMASK_ULL(36, 0); \ > - __ta |= (unsigned long)(ttl) << 37; \ > - __ta |= (unsigned long)(num) << 39; \ > - __ta |= (unsigned long)(scale) << 44; \ > - __ta |= get_trans_granule() << 46; \ > - __ta |= (unsigned long)(asid) << 48; \ > - __ta; \ > +#define __TLBI_VADDR_RANGE(addr, asid, scale, num, ttl) \ > + ({ \ > + unsigned long __ta = (addr) >> PAGE_SHIFT; \ > + unsigned long __ttl = (ttl >= 1 && ttl <= 3) ? ttl : 0; \ And here, set __ttl to 0 if TLBI_TTL_UNKNOWN. Otherwise it looks fine: Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Thanks for the review! On 12/04/2023 16:47, Catalin Marinas wrote: > On Mon, Mar 06, 2023 at 07:54:27PM +0000, Ryan Roberts wrote: >> FEAT_LPA2 impacts tlb invalidation in 2 ways; Firstly, the TTL field in >> the non-range tlbi instructions can now validly take a 0 value for the >> 4KB granule (this is due to the extra level of translation). Secondly, >> the BADDR field in the range tlbi instructions must be aligned to 64KB >> when LPA2 is in use (TCR.DS=1). Changes are required for tlbi to >> continue to operate correctly when LPA2 is in use. >> >> KVM only uses the non-range (__tlbi_level()) routines. Therefore we only >> solve the first problem with this patch. > > There are some patches on the list to add support for range invalidation > in KVM: > > https://lore.kernel.org/r/20230206172340.2639971-1-rananta@google.com I have the required change for range invalidation at: https://gitlab.arm.com/linux-arm/linux-rr/-/commit/38628decb785aea42a349a857b9f8a65a19e9c2b. But I didn't include it in this submission because it would be dead code until either the patches you point out land, or Ard's patches land. Also, the implementation I did uses the CPU feature to determine which variant to apply, and since the kernel is not using LPA2 yet, it would give the wrong answer for the case where LPA2 is supported by the system. I think this patch (or similar) should be included with Ard's changes. What's your view? > >> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h >> index 412a3b9a3c25..67dd47df42d5 100644 >> --- a/arch/arm64/include/asm/tlbflush.h >> +++ b/arch/arm64/include/asm/tlbflush.h >> @@ -93,19 +93,22 @@ static inline unsigned long get_trans_granule(void) >> * When ARMv8.4-TTL exists, TLBI operations take an additional hint for >> * the level at which the invalidation must take place. If the level is >> * wrong, no invalidation may take place. In the case where the level >> - * cannot be easily determined, a 0 value for the level parameter will >> - * perform a non-hinted invalidation. >> + * cannot be easily determined, the value TLBI_TTL_UNKNOWN will perform >> + * a non-hinted invalidation. Any provided level outside the hint range >> + * will also cause fall-back to non-hinted invalidation. >> * >> * For Stage-2 invalidation, use the level values provided to that effect >> * in asm/stage2_pgtable.h. >> */ >> #define TLBI_TTL_MASK GENMASK_ULL(47, 44) >> >> +#define TLBI_TTL_UNKNOWN (-1) >> + >> #define __tlbi_level(op, addr, level) do { \ >> u64 arg = addr; \ >> \ >> if (cpus_have_const_cap(ARM64_HAS_ARMv8_4_TTL) && \ >> - level) { \ >> + level >= 0 && level <= 3) { \ > > I'd just use level != TLBI_TTL_UNKNOWN here. I don't think that is correct, since if/when level -2 gets added, TLBI_TTL_UNKNOWN would likely be changed to -2, and with your logic, you would allow level=-1 through and ttl = -1 & 3 = 3. Callers will call this with the actual level [-1, 3] and the intent here is to use a hint where the instruction supports it [0, 3]. If you're concerned about the 2 comparisons, how about leaving "level >= 0" and removing "level <= 3"? > >> u64 ttl = level & 3; \ >> ttl |= get_trans_granule() << 2; \ >> arg &= ~TLBI_TTL_MASK; \ >> @@ -133,16 +136,17 @@ static inline unsigned long get_trans_granule(void) >> * [BADDR, BADDR + (NUM + 1) * 2^(5*SCALE + 1) * PAGESIZE) >> * >> */ >> -#define __TLBI_VADDR_RANGE(addr, asid, scale, num, ttl) \ >> - ({ \ >> - unsigned long __ta = (addr) >> PAGE_SHIFT; \ >> - __ta &= GENMASK_ULL(36, 0); \ >> - __ta |= (unsigned long)(ttl) << 37; \ >> - __ta |= (unsigned long)(num) << 39; \ >> - __ta |= (unsigned long)(scale) << 44; \ >> - __ta |= get_trans_granule() << 46; \ >> - __ta |= (unsigned long)(asid) << 48; \ >> - __ta; \ >> +#define __TLBI_VADDR_RANGE(addr, asid, scale, num, ttl) \ >> + ({ \ >> + unsigned long __ta = (addr) >> PAGE_SHIFT; \ >> + unsigned long __ttl = (ttl >= 1 && ttl <= 3) ? ttl : 0; \ > > And here, set __ttl to 0 if TLBI_TTL_UNKNOWN. Same argument as above. > > Otherwise it looks fine: > > Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
diff --git a/arch/arm64/include/asm/tlb.h b/arch/arm64/include/asm/tlb.h index c995d1f4594f..2cb458f6b98f 100644 --- a/arch/arm64/include/asm/tlb.h +++ b/arch/arm64/include/asm/tlb.h @@ -22,15 +22,16 @@ static void tlb_flush(struct mmu_gather *tlb); #include <asm-generic/tlb.h> /* - * get the tlbi levels in arm64. Default value is 0 if more than one - * of cleared_* is set or neither is set. + * get the tlbi levels in arm64. Default value is TLBI_TTL_UNKNOWN if more than + * one of cleared_* is set or neither is set - this elides the level hinting to + * the hardware. * Arm64 doesn't support p4ds now. */ static inline int tlb_get_level(struct mmu_gather *tlb) { /* The TTL field is only valid for the leaf entry. */ if (tlb->freed_tables) - return 0; + return TLBI_TTL_UNKNOWN; if (tlb->cleared_ptes && !(tlb->cleared_pmds || tlb->cleared_puds || @@ -47,7 +48,7 @@ static inline int tlb_get_level(struct mmu_gather *tlb) tlb->cleared_p4ds)) return 1; - return 0; + return TLBI_TTL_UNKNOWN; } static inline void tlb_flush(struct mmu_gather *tlb) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index 412a3b9a3c25..67dd47df42d5 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -93,19 +93,22 @@ static inline unsigned long get_trans_granule(void) * When ARMv8.4-TTL exists, TLBI operations take an additional hint for * the level at which the invalidation must take place. If the level is * wrong, no invalidation may take place. In the case where the level - * cannot be easily determined, a 0 value for the level parameter will - * perform a non-hinted invalidation. + * cannot be easily determined, the value TLBI_TTL_UNKNOWN will perform + * a non-hinted invalidation. Any provided level outside the hint range + * will also cause fall-back to non-hinted invalidation. * * For Stage-2 invalidation, use the level values provided to that effect * in asm/stage2_pgtable.h. */ #define TLBI_TTL_MASK GENMASK_ULL(47, 44) +#define TLBI_TTL_UNKNOWN (-1) + #define __tlbi_level(op, addr, level) do { \ u64 arg = addr; \ \ if (cpus_have_const_cap(ARM64_HAS_ARMv8_4_TTL) && \ - level) { \ + level >= 0 && level <= 3) { \ u64 ttl = level & 3; \ ttl |= get_trans_granule() << 2; \ arg &= ~TLBI_TTL_MASK; \ @@ -133,16 +136,17 @@ static inline unsigned long get_trans_granule(void) * [BADDR, BADDR + (NUM + 1) * 2^(5*SCALE + 1) * PAGESIZE) * */ -#define __TLBI_VADDR_RANGE(addr, asid, scale, num, ttl) \ - ({ \ - unsigned long __ta = (addr) >> PAGE_SHIFT; \ - __ta &= GENMASK_ULL(36, 0); \ - __ta |= (unsigned long)(ttl) << 37; \ - __ta |= (unsigned long)(num) << 39; \ - __ta |= (unsigned long)(scale) << 44; \ - __ta |= get_trans_granule() << 46; \ - __ta |= (unsigned long)(asid) << 48; \ - __ta; \ +#define __TLBI_VADDR_RANGE(addr, asid, scale, num, ttl) \ + ({ \ + unsigned long __ta = (addr) >> PAGE_SHIFT; \ + unsigned long __ttl = (ttl >= 1 && ttl <= 3) ? ttl : 0; \ + __ta &= GENMASK_ULL(36, 0); \ + __ta |= __ttl << 37; \ + __ta |= (unsigned long)(num) << 39; \ + __ta |= (unsigned long)(scale) << 44; \ + __ta |= get_trans_granule() << 46; \ + __ta |= (unsigned long)(asid) << 48; \ + __ta; \ }) /* These macros are used by the TLBI RANGE feature. */ @@ -215,12 +219,16 @@ static inline unsigned long get_trans_granule(void) * CPUs, ensuring that any walk-cache entries associated with the * translation are also invalidated. * - * __flush_tlb_range(vma, start, end, stride, last_level) + * __flush_tlb_range(vma, start, end, stride, last_level, tlb_level) * Invalidate the virtual-address range '[start, end)' on all * CPUs for the user address space corresponding to 'vma->mm'. * The invalidation operations are issued at a granularity * determined by 'stride' and only affect any walk-cache entries - * if 'last_level' is equal to false. + * if 'last_level' is equal to false. tlb_level is the level at + * which the invalidation must take place. If the level is wrong, + * no invalidation may take place. In the case where the level + * cannot be easily determined, the value TLBI_TTL_UNKNOWN will + * perform a non-hinted invalidation. * * * Finally, take a look at asm/tlb.h to see how tlb_flush() is implemented @@ -366,9 +374,10 @@ static inline void flush_tlb_range(struct vm_area_struct *vma, /* * We cannot use leaf-only invalidation here, since we may be invalidating * table entries as part of collapsing hugepages or moving page tables. - * Set the tlb_level to 0 because we can not get enough information here. + * Set the tlb_level to TLBI_TTL_UNKNOWN because we can not get enough + * information here. */ - __flush_tlb_range(vma, start, end, PAGE_SIZE, false, 0); + __flush_tlb_range(vma, start, end, PAGE_SIZE, false, TLBI_TTL_UNKNOWN); } static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end)
FEAT_LPA2 impacts tlb invalidation in 2 ways; Firstly, the TTL field in the non-range tlbi instructions can now validly take a 0 value for the 4KB granule (this is due to the extra level of translation). Secondly, the BADDR field in the range tlbi instructions must be aligned to 64KB when LPA2 is in use (TCR.DS=1). Changes are required for tlbi to continue to operate correctly when LPA2 is in use. KVM only uses the non-range (__tlbi_level()) routines. Therefore we only solve the first problem with this patch. It is solved by always adding the level hint if the level is between [0, 3] (previously anything other than 0 was hinted, which breaks in the new level -1 case from kvm). When running on non-LPA2 HW, 0 is still safe to hint as the HW will fall back to non-hinted. While we are at it, we replace the notion of 0 being the non-hinted seninel with a macro, TLBI_TTL_UNKNOWN. This means callers won't need updating if/when translation depth increases in future. Signed-off-by: Ryan Roberts <ryan.roberts@arm.com> --- arch/arm64/include/asm/tlb.h | 9 ++++--- arch/arm64/include/asm/tlbflush.h | 43 +++++++++++++++++++------------ 2 files changed, 31 insertions(+), 21 deletions(-)