diff mbox series

[v2,02/12] arm64/mm: Add FEAT_LPA2 specific ID_AA64MMFR0.TGRAN[2]

Message ID 20230306195438.1557851-3-ryan.roberts@arm.com (mailing list archive)
State New, archived
Headers show
Series KVM: arm64: Support FEAT_LPA2 at hyp s1 and vm s2 | expand

Commit Message

Ryan Roberts March 6, 2023, 7:54 p.m. UTC 
From: Anshuman Khandual <anshuman.khandual@arm.com>

PAGE_SIZE support is tested against possible minimum and maximum values for
its respective ID_AA64MMFR0.TGRAN field, depending on whether it is signed
or unsigned. But then FEAT_LPA2 implementation needs to be validated for 4K
and 16K page sizes via feature specific ID_AA64MMFR0.TGRAN values. Hence it
adds FEAT_LPA2 specific ID_AA64MMFR0.TGRAN[2] values per ARM ARM (0487G.A).

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
---
 arch/arm64/include/asm/sysreg.h | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Catalin Marinas April 12, 2023, 4:27 p.m. UTC | #1 
On Mon, Mar 06, 2023 at 07:54:28PM +0000, Ryan Roberts wrote:
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 9e3ecba3c4e6..7f708eecc3ad 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -609,10 +609,12 @@
>  
>  /* id_aa64mmfr0 */
>  #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN	0x0
> +#define ID_AA64MMFR0_EL1_TGRAN4_LPA2		ID_AA64MMFR0_EL1_TGRAN4_52_BIT
>  #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX	0x7
>  #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN	0x0
>  #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX	0x7
>  #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN	0x1
> +#define ID_AA64MMFR0_EL1_TGRAN16_LPA2		ID_AA64MMFR0_EL1_TGRAN16_52_BIT
>  #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX	0xf

This patch evolved a bit since I first acked it in Anshuman's series. I
can't find any trace of ID_AA64MMFR0_EL1_TGRAN4_52_BIT in the kernel. Is
it introduced in a later patch?
Ryan Roberts April 13, 2023, 8:16 a.m. UTC | #2 
On 12/04/2023 17:27, Catalin Marinas wrote:
> On Mon, Mar 06, 2023 at 07:54:28PM +0000, Ryan Roberts wrote:
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index 9e3ecba3c4e6..7f708eecc3ad 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -609,10 +609,12 @@
>>  
>>  /* id_aa64mmfr0 */
>>  #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN	0x0
>> +#define ID_AA64MMFR0_EL1_TGRAN4_LPA2		ID_AA64MMFR0_EL1_TGRAN4_52_BIT
>>  #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX	0x7
>>  #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN	0x0
>>  #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX	0x7
>>  #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN	0x1
>> +#define ID_AA64MMFR0_EL1_TGRAN16_LPA2		ID_AA64MMFR0_EL1_TGRAN16_52_BIT
>>  #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX	0xf
> 
> This patch evolved a bit since I first acked it in Anshuman's series. I
> can't find any trace of ID_AA64MMFR0_EL1_TGRAN4_52_BIT in the kernel. Is
> it introduced in a later patch?
> 

It's autogenerated as part of the sysreg magic. Ends up in
arch/arm64/include/generated/asm/sysreg-defs.h.
Catalin Marinas April 13, 2023, 4:54 p.m. UTC | #3 
On Thu, Apr 13, 2023 at 09:16:03AM +0100, Ryan Roberts wrote:
> On 12/04/2023 17:27, Catalin Marinas wrote:
> > On Mon, Mar 06, 2023 at 07:54:28PM +0000, Ryan Roberts wrote:
> >> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> >> index 9e3ecba3c4e6..7f708eecc3ad 100644
> >> --- a/arch/arm64/include/asm/sysreg.h
> >> +++ b/arch/arm64/include/asm/sysreg.h
> >> @@ -609,10 +609,12 @@
> >>  
> >>  /* id_aa64mmfr0 */
> >>  #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN	0x0
> >> +#define ID_AA64MMFR0_EL1_TGRAN4_LPA2		ID_AA64MMFR0_EL1_TGRAN4_52_BIT
> >>  #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX	0x7
> >>  #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN	0x0
> >>  #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX	0x7
> >>  #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN	0x1
> >> +#define ID_AA64MMFR0_EL1_TGRAN16_LPA2		ID_AA64MMFR0_EL1_TGRAN16_52_BIT
> >>  #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX	0xf
> > 
> > This patch evolved a bit since I first acked it in Anshuman's series. I
> > can't find any trace of ID_AA64MMFR0_EL1_TGRAN4_52_BIT in the kernel. Is
> > it introduced in a later patch?
> 
> It's autogenerated as part of the sysreg magic. Ends up in
> arch/arm64/include/generated/asm/sysreg-defs.h.

Ah, I keep forgetting this (I usually build the kernel in a different
directory, so grep doesn't encounter it).
diff mbox series

Patch

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 9e3ecba3c4e6..7f708eecc3ad 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -609,10 +609,12 @@ 
 
 /* id_aa64mmfr0 */
 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN	0x0
+#define ID_AA64MMFR0_EL1_TGRAN4_LPA2		ID_AA64MMFR0_EL1_TGRAN4_52_BIT
 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX	0x7
 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN	0x0
 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX	0x7
 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN	0x1
+#define ID_AA64MMFR0_EL1_TGRAN16_LPA2		ID_AA64MMFR0_EL1_TGRAN16_52_BIT
 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX	0xf
 
 #define ARM64_MIN_PARANGE_BITS		32
@@ -620,6 +622,7 @@ 
 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT	0x0
 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE		0x1
 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN		0x2
+#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2		0x3
 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX		0x7
 
 #ifdef CONFIG_ARM64_PA_BITS_52
@@ -630,11 +633,13 @@ 
 
 #if defined(CONFIG_ARM64_4K_PAGES)
 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN4_SHIFT
+#define ID_AA64MMFR0_EL1_TGRAN_LPA2		ID_AA64MMFR0_EL1_TGRAN4_52_BIT
 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX
 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT
 #elif defined(CONFIG_ARM64_16K_PAGES)
 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN16_SHIFT
+#define ID_AA64MMFR0_EL1_TGRAN_LPA2		ID_AA64MMFR0_EL1_TGRAN16_52_BIT
 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN
 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX
 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT