From patchwork Mon Mar 20 04:49:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 13180721 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0D3F8C6FD1D for ; Mon, 20 Mar 2023 04:50:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=SwsD1j3pSc/+BmmX99Uh8KpMKgUywdKDuKiyDlzIyjQ=; b=gWDEknj4/Kx+Vm CozWVGZBrdXau036tQ8fk2BC2xtvlHPDVw1B7M6NO/I5tQYCST2vxdAS4er1uK1YutmJqrySGElGG Rl+YuaWcD+jzYBh7JXKKOZYJpuCVUmq6dwO0fMwEo8gO5izbr0qurIS7hyjMS3ckhyzV5YnNuf8wQ wckVH2vSs3Ua5bfYZwvCFAB6ML1xgCUPpSYLvJOHLTj1oug86NmOZMGLpf3xEUOJ5qXjqIYLMnN6j 5OmfwhyqkfvaaMUDa65hyE1FsR1xJVTG/mxeLqxL30rbTeIra3UYpEfyiH/5JfoUrsVgDLc0utgNy Ky1t/R6akpAPHt72C6yg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pe7T2-0085CD-34; Mon, 20 Mar 2023 04:49:56 +0000 Received: from fllv0015.ext.ti.com ([198.47.19.141]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pe7T0-0085BQ-0n for linux-arm-kernel@lists.infradead.org; Mon, 20 Mar 2023 04:49:56 +0000 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32K4ndKf118247; Sun, 19 Mar 2023 23:49:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1679287779; bh=TM9MDixLBitTiS5DwNdvv6gnMOmxa83dc/dRIltZTCQ=; h=From:To:CC:Subject:Date; b=A7vJZWyDIuHjuFtBGOtBylC8EZ8pqKB54AYEPkdRmvQM3/6fI0GA1NnptnRiTdX9r M0YhKlY0hSXLlskZo2gcGcwk9ExlzB4nnfxlug9lJ+RgfrFA/BLr4R8zbv0eisX00f g5MnGe1IWi5rYn0Ys6Pp+hjIAe+PePf0dp31x4oc= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32K4nd2M058025 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sun, 19 Mar 2023 23:49:39 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Sun, 19 Mar 2023 23:49:39 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Sun, 19 Mar 2023 23:49:39 -0500 Received: from uda0132425.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32K4naix022696; Sun, 19 Mar 2023 23:49:37 -0500 From: Vignesh Raghavendra To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski CC: , , Subject: [PATCH 1/2] arm64: dts: ti: k3-am625: Correct L2 cache size to 512KB Date: Mon, 20 Mar 2023 10:19:34 +0530 Message-ID: <20230320044935.2512288-1-vigneshr@ti.com> X-Mailer: git-send-email 2.40.0 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230319_214954_365608_FA55283B X-CRM114-Status: GOOD ( 10.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Per AM62x SoC datasheet[0] L2 cache is 512KB. [0] https://www.ti.com/lit/gpn/am625 Page 1. Fixes: f1d17330a5be ("arm64: dts: ti: Introduce base support for AM62x SoC") Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am625.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/k3-am625.dtsi index acc7f8ab6426..4193c2b3eed6 100644 --- a/arch/arm64/boot/dts/ti/k3-am625.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi @@ -148,7 +148,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-unified; cache-level = <2>; - cache-size = <0x40000>; + cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; };