From patchwork Mon Mar 20 13:18:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 13181226 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 963BBC7618A for ; Mon, 20 Mar 2023 13:20:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=0pbFQfAOPIQRyfnbR4AZq6ZJeouTH1aQGcfASWU63s0=; b=Jn+rng4c5TtFqr 06zQJpyGuCU+57gRZyTRxzEocyw/H0L4P+6ETqpa4sICyStZAlaBC5zqfwNZ+ZeNu47TnqYlwBts7 fawUsJpp7fuiwxM7iQ9DkKww0einLZfDa6iDyuirD3AjkNwX7DZ3/LWCh4V0DdLLCdJ5jKMwz23nt rRfNerRZRsOkAvJS+6Ra11Y9PcZdTtDN7+aKgjAEaP/DQWkcIvXsBF69y4AP2QHJ4bGjd/+Zv3HuZ lD/Bvy5I/pejAQNs7viB9zKfeHhHk4/7ZGKh5v/xZxpZx/4Pfc9ZFXJi8Au8vijubKKHvw2R6AahO RS3ZRLhCzEvJmOBA4xEA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1peFQK-0096CJ-0R; Mon, 20 Mar 2023 13:19:40 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1peFPm-0095sJ-1V for linux-arm-kernel@lists.infradead.org; Mon, 20 Mar 2023 13:19:09 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 08A72614EE; Mon, 20 Mar 2023 13:19:06 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 87F56C433EF; Mon, 20 Mar 2023 13:19:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1679318345; bh=8z1nx5KS1slzGDFVSb0GsTLShVL5cQTShTJwdUf8fg0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oAfbQMMyDzR0s9Gh1OoQwe6ZFYOGLb3Vv65hfXVstOubQ3LMl7CZf2vik9FEcP+VS FmvdPGlgX/X+3qFagpQCLV9ZDExE9jatUSYnpnESww422tspGCzVNl8/8pQwGFTSVZ v3dLDn+ncBWuYedx+COZ4IOFpiUlkG+N9b1Kku92l+LgM+IFGUrFScXTf3oyoY7XCV Ht0r9ggIC6Z3giRgD9vbRCu7lPsU4OOvnXHXlz/7yUY8MP5S3TI14AkTFdbIg8qMg6 44U5AGnI1yhPcupyNL3TH25OB1I6NfksiJ/voKubyJl0uWki2pRamQwtOZIuQOhijY 5/yxeLJ6FFs7w== From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, linux@armlinux.org.uk Cc: Ard Biesheuvel , Frederic Weisbecker , Guenter Roeck , Peter Zijlstra , Linus Walleij , Arnd Bergmann Subject: [PATCH v4 06/12] ARM: vfp: Remove workaround for Feroceon CPUs Date: Mon, 20 Mar 2023 14:18:39 +0100 Message-Id: <20230320131845.3138015-7-ardb@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230320131845.3138015-1-ardb@kernel.org> References: <20230320131845.3138015-1-ardb@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3724; i=ardb@kernel.org; h=from:subject; bh=8z1nx5KS1slzGDFVSb0GsTLShVL5cQTShTJwdUf8fg0=; b=owGbwMvMwCFmkMcZplerG8N4Wi2JIUUiVsdr37PFx25qmxcZ6TmWvRR0iBdQefJM7W+wuP7Co MjrjJs6SlkYxDgYZMUUWQRm/3238/REqVrnWbIwc1iZQIYwcHEKwETKDRkZVn4+GrDhkxmnt8Zp 39gPwhcUo2f2O7/ZHHvaUuah+NT7Wxh+syrdi5m/fiV/KwPzmYti0hy7z+1YVH1ol/kb3YBPiYX 6zAA= X-Developer-Key: i=ardb@kernel.org; a=openpgp; fpr=F43D03328115A198C90016883D200E9CA6329909 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230320_061906_584066_17FE39EE X-CRM114-Status: GOOD ( 20.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Feroceon CPUs have a non-standard implementation of VFP which reports synchronous VFP exceptions using the async VFP flag. This requires a workaround which is difficult to reconcile with other implementations, making it tricky to support both versions in a single image. Since this is a v5 CPU, it is not supported by armhf and so the likelihood that anybody is using this with recent distros/kernels and rely on the VFP at the same time is extremely low. So let's just disable VFP support on these cores, so we can remove the workaround. This will help future development to support v5 and v6 CPUs with a single kernel image. Signed-off-by: Ard Biesheuvel Reviewed-by: Linus Walleij Acked-by: Nicolas Pitre --- arch/arm/mm/proc-feroceon.S | 4 ++++ arch/arm/vfp/vfphw.S | 4 ---- arch/arm/vfp/vfpmodule.c | 8 +++++--- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index 61ce82aca6f0d603..072ff9b451f846bf 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S @@ -56,6 +56,10 @@ ENTRY(cpu_feroceon_proc_init) movne r2, r2, lsr #2 @ turned into # of sets sub r2, r2, #(1 << 5) stmia r1, {r2, r3} +#ifdef CONFIG_VFP + mov r1, #1 @ disable quirky VFP + str_l r1, VFP_arch_feroceon, r2 +#endif ret lr /* diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S index 4d8478264d82b3d2..8049c6830eeb1380 100644 --- a/arch/arm/vfp/vfphw.S +++ b/arch/arm/vfp/vfphw.S @@ -110,7 +110,6 @@ ENTRY(vfp_support_entry) beq vfp_reload_hw @ then the hw state needs reloading VFPFSTMIA r4, r5 @ save the working registers VFPFMRX r5, FPSCR @ current status -#ifndef CONFIG_CPU_FEROCEON tst r1, #FPEXC_EX @ is there additional state to save? beq 1f VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set) @@ -118,7 +117,6 @@ ENTRY(vfp_support_entry) beq 1f VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present) 1: -#endif stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2 vfp_reload_hw: @@ -153,7 +151,6 @@ vfp_reload_hw: VFPFLDMIA r10, r5 @ reload the working registers while @ FPEXC is in a safe state ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2 -#ifndef CONFIG_CPU_FEROCEON tst r1, #FPEXC_EX @ is there additional state to restore? beq 1f VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set) @@ -161,7 +158,6 @@ vfp_reload_hw: beq 1f VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present) 1: -#endif VFPFMXR FPSCR, r5 @ restore status @ The context stored in the VFP hardware is up to date with this thread diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index 039c8dab990699e2..dd31d13ca1d8fc8a 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -42,7 +42,11 @@ static bool have_vfp __ro_after_init; * Used in startup: set to non-zero if VFP checks fail * After startup, holds VFP architecture */ -static unsigned int __initdata VFP_arch; +static unsigned int VFP_arch; + +#ifdef CONFIG_CPU_FEROCEON +extern unsigned int VFP_arch_feroceon __alias(VFP_arch); +#endif /* * The pointer to the vfpstate structure of the thread which currently @@ -357,14 +361,12 @@ void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs) } if (fpexc & FPEXC_EX) { -#ifndef CONFIG_CPU_FEROCEON /* * Asynchronous exception. The instruction is read from FPINST * and the interrupted instruction has to be restarted. */ trigger = fmrx(FPINST); regs->ARM_pc -= 4; -#endif } else if (!(fpexc & FPEXC_DEX)) { /* * Illegal combination of bits. It can be caused by an