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Tue, 21 Mar 2023 02:07:13 -0500 From: Parth Gajjar To: , , CC: , , , , , , , Parth Gajjar Subject: [PATCH v2 2/2] arm64: zynqmp: Add mali-400 gpu node for zynqmp Date: Tue, 21 Mar 2023 00:06:19 -0700 Message-ID: <20230321070619.29440-3-parth.gajjar@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230321070619.29440-1-parth.gajjar@amd.com> References: <20230321070619.29440-1-parth.gajjar@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT066:EE_|SN7PR12MB6792:EE_ X-MS-Office365-Filtering-Correlation-Id: 44a3cb08-c419-4ff7-ccee-08db29dae71d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: C7jSuW3LV0NGHus0yruSdxVzyeVmb0ar9F1n1iNBBoucw6krPbXjMfwcZ2OI37pu1vHJ3zUX2t78BVdMgpK0WPkEbU8LRF2TOsjifYfgZo+BO05VCVVRic5lnwUr2fSJrFhanIkWani98iMXMu8bwbBThXI1HCH3nVUeUxwYzFwThYHfpdUtRCf29Jqd9QTUiDDyWmFzdGX3QiJPQs2136NlwtJqI3P5JeIGnMKnG0Ho3aoyF5Qy/LcoL5EfhigH/o/vDoYoROkGaL/n/8v/Z8GnDoqhxW6gaHvQjGiT+FXAnNSsomT9pmQBKF/yQxwRasrLMJIXGNDze/p5j6vC9QV6HIjk5pObZ7Wrt/eaciTysfi7xbVGA+M9Z4xQAeVmG/G/eqVi6nlJnfR6GrL7YZ+UBPQU5cl8Q4eAwEU0MhufXYG0IpZxr8Rx2XpXyP+hren8Lx+1xe5LLunlWh2CjjzjEkgUza8HLIJNyF9EFt5vZkqq5dooyGxCpFW06PPNfXUjDrHvWXRYb1wEEt9b4Ws7D/gYaaJO1wxKwMDMw5uYyP95pleB1QFIAdK/mCXKNq9KuMl6XdmP6hFJtz2MkGRlT5I7Bvxxdw6VZ2BIVw3sewVfM2Et/8FY8HOtp0tyyj9sM/HIPdmbu1BOxmbRSLpR39CMOUrXJmi8hgUECl/ZRXlPcuA5lTVWQnTFqMghEp3bfiYyoD5gDfcnSFKzS31EEObztPcgeiSQ/fwIYSk= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(396003)(39860400002)(376002)(346002)(136003)(451199018)(46966006)(40470700004)(36840700001)(41300700001)(40480700001)(44832011)(336012)(8936002)(5660300002)(40460700003)(36860700001)(47076005)(426003)(356005)(2906002)(82740400003)(186003)(82310400005)(2616005)(478600001)(81166007)(110136005)(316002)(83380400001)(26005)(86362001)(1076003)(54906003)(4326008)(36756003)(70206006)(70586007)(8676002)(36900700001);DIR:OUT;SFP:1101; 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Enabled gpu node for xilinx boards. Signed-off-by: Parth Gajjar Signed-off-by: Vishal Sagar --- arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 4 ++++ .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 3 +++ .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 12 ++++++++++++ 11 files changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 3e9979ab60bb..5e7e1bf5b811 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -95,6 +95,10 @@ &fpd_dma_chan8 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; +&gpu { + clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>; +}; + &lpd_dma_chan1 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 20e83ca47b5d..34412304d09f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -287,3 +287,7 @@ &gpio { "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; + +&gpu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index b05be2552826..f89ef2afcd9e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -108,6 +108,9 @@ &gpio { pinctrl-0 = <&pinctrl_gpio_default>; }; +&gpu { + status = "okay"; +}; &i2c1 { status = "okay"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts index 05a2b79738af..6e0106bf1294 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts @@ -152,6 +152,10 @@ &gpio { status = "okay"; }; +&gpu { + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; status = "okay"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index 6948fd40554b..c74bc3ff703b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -161,6 +161,10 @@ &gpio { "", "", "", ""; }; +&gpu { + status = "okay"; +}; + &i2c1 { status = "okay"; pinctrl-names = "default", "gpio"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 5fd6b70a154a..13c43324f1d2 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -216,6 +216,10 @@ &gpio { pinctrl-0 = <&pinctrl_gpio_default>; }; +&gpu { + status = "okay"; +}; + &i2c0 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index bd8f20f3223d..485585c491f4 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -122,6 +122,10 @@ &gpio { status = "okay"; }; +&gpu { + status = "okay"; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 96feaad30166..44ec9edd2452 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -127,6 +127,10 @@ &gpio { status = "okay"; }; +&gpu { + status = "okay"; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 24a252317150..09773b7200f8 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -227,6 +227,10 @@ &gpio { pinctrl-0 = <&pinctrl_gpio_default>; }; +&gpu { + status = "okay"; +}; + &i2c0 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index d685d8fbc36a..e0305dcbb010 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -187,6 +187,10 @@ &gpio { pinctrl-0 = <&pinctrl_gpio_default>; }; +&gpu { + status = "okay"; +}; + &i2c0 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 153db59dc4b3..bb0d0be30aa0 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -411,6 +411,18 @@ gic: interrupt-controller@f9010000 { interrupts = <1 9 0xf04>; }; + gpu: gpu@fd4b0000 { + status = "disabled"; + compatible = "xlnx,zynqmp-mali", "arm,mali-400"; + reg = <0x0 0xfd4b0000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0 132 4>, <0 132 4>, <0 132 4>, + <0 132 4>, <0 132 4>, <0 132 4>; + interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1"; + clock-names = "bus", "core"; + power-domains = <&zynqmp_firmware PD_GPU>; + }; + /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access.