From patchwork Mon Apr 3 00:37:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13197588 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0AB42C761AF for ; Mon, 3 Apr 2023 00:39:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=QmVqtAEuJsYzBP9h+r5/as+014PCIdiP8AEGtVQHae0=; b=2xoFfnT9T5KjB5vSEJw6PKRlAC 1NfPzBiZpkeDWiRmnOBd9ttTixSOwyXfvfTIYzHw9eLaZNm05sZHxQwoF5Elyd6VhkVD8CzLJ95qW 27EdCrQrsyMHAKdnqUTJJNy11LimeU7qKSzuv8rBWBnuVoprMKvzsdkQQ9rUOKXJAuE7VrPt3ZJWM C6g/QmheESQGcpV5FA75WAmMNjAlSerD9FCXrLQhkbyIeA2OpAqquMz1PM9ZxI9FvDB0jXtRr0XV2 CtT22Yopi/veQyRBLL+GDfhLE1bT8uTCrq2MYnBwmH3S0ta6qeIRwtmUp4Tvm6Ne4EN54Bex0kVQ8 QGOBIGKw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pj8CT-00DWMJ-0L; Mon, 03 Apr 2023 00:37:33 +0000 Received: from mail-pf1-x449.google.com ([2607:f8b0:4864:20::449]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pj8CP-00DWKm-0Y for linux-arm-kernel@lists.infradead.org; Mon, 03 Apr 2023 00:37:30 +0000 Received: by mail-pf1-x449.google.com with SMTP id x68-20020a628647000000b0062624c52117so12508158pfd.14 for ; Sun, 02 Apr 2023 17:37:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; t=1680482247; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=n9hPEYzgNXRlO9uoyqPqxQh7PdJy06R+RDjdkmdpz/c=; b=NRtbxi5vrt9eFXSSXs1twqJTwK/3Nket9yy3+qA3Ojsm17zd1APFPfJECa5atNFHQj I7pa4qqiZr8xG/dNvazCN94z6uTO7gUjY2+6T4lZwnEYt9grt6Qez8JflWMZF9SvaVrB DYI79IDdOSY5GKqu8eKGn6WHZCqt6R3IY3pB3HTfpxE7FSiovK8QXN0WadG5+yxCL58n way45DpLZgkVGHd+QDzu4I0skN4V9OjHfYRaGJIkcjinyTj19Cl8ehZUy0MStUQhIsQ5 jyu74KvTkJVwt+QaZHkHFaxjAeObyoRQOfQfAYIdQls2+cxf8jgcBLsXXLB0bdQ5DXQ8 aLAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680482247; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=n9hPEYzgNXRlO9uoyqPqxQh7PdJy06R+RDjdkmdpz/c=; b=29yH3R/PtphdW5I/IfovL513wrf/d2C7pY4svPtH2N7h0v3HbMOJwl4umZC/4uCiGu eBbNppmfe6Y615e4cSmyitNcOWBuAxTYG683uRl1z5SayCzJUW+bb2Y5DeclxVDhik8U 0r1G5GGS/r+IHrIxdc8LgJzpzFDDGrt9knxilnO51bvy9RvbkMptqOvaKaW4blTz/5kB MjSlXpiDlKMXCK88kCXlTNGYcI0woD1X8M3NrZNRRewb1HtzSwqHkamlRkeWBqrBOz7Z LOe9qtWptH7b1oh6j1tTmLOG6/Rw+ikEJmSo+IzvtXzMK8PAKv/FEHFNptQPyzYUkRM1 r/Gg== X-Gm-Message-State: AAQBX9eyp0+BAQTMEmvxoVEXgEMmdi5e8JXl2zmDudTrreLyvZnpZOJq afIbzF+0SojKor6gL/L4q5h08G1HgqEiDLPxNQ== X-Google-Smtp-Source: AKy350YvYZD4xlcGV3J9XFyvItXlNeRUnWMXoeihnesDdqKMO8h8/ozUdcGAtvsc5vhiQSgXaBt6M2uddrnRjkBf+w== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a05:6a00:2d8f:b0:62d:ccc4:2e03 with SMTP id fb15-20020a056a002d8f00b0062dccc42e03mr6387878pfb.4.1680482247647; Sun, 02 Apr 2023 17:37:27 -0700 (PDT) Date: Mon, 3 Apr 2023 00:37:22 +0000 In-Reply-To: <20230403003723.3199828-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230403003723.3199828-1-jingzhangos@google.com> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog Message-ID: <20230403003723.3199828-2-jingzhangos@google.com> Subject: [PATCH v2 1/2] KVM: arm64: Enable writable for ID_AA64DFR0_EL1 From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Jing Zhang X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230402_173729_207793_0C39780F X-CRM114-Status: GOOD ( 14.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Since number of context-aware breakpoints must be no more than number of supported breakpoints according to Arm ARM, return an error if userspace tries to set CTX_CMPS field to such value. Signed-off-by: Jing Zhang --- arch/arm64/kvm/id_regs.c | 43 ++++++++++++++++++++++------------------ 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c index 395eaf84a0ab..7ca76a167c90 100644 --- a/arch/arm64/kvm/id_regs.c +++ b/arch/arm64/kvm/id_regs.c @@ -355,10 +355,15 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, u64 val) { - u8 pmuver, host_pmuver; + u8 pmuver, host_pmuver, brps, ctx_cmps; bool valid_pmu; int ret; + brps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_BRPs), val); + ctx_cmps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_CTX_CMPs), val); + if (ctx_cmps > brps) + return -EINVAL; + host_pmuver = kvm_arm_pmu_get_pmuver_limit(); /* @@ -377,28 +382,28 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, if (kvm_vcpu_has_pmu(vcpu) != valid_pmu) return -EINVAL; - if (valid_pmu) { - mutex_lock(&vcpu->kvm->arch.config_lock); - ret = set_id_reg(vcpu, rd, val); - if (ret) { - mutex_unlock(&vcpu->kvm->arch.config_lock); - return ret; - } + if (!valid_pmu) { + /* Igore the pmuver field in val */ + pmuver = FIELD_GET(ID_AA64DFR0_EL1_PMUVer_MASK, read_id_reg(vcpu, rd)); + val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; + val |= FIELD_PREP(ID_AA64DFR0_EL1_PMUVer_MASK, pmuver); + } - IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); - IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= - FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), pmuver_to_perfmon(pmuver)); + mutex_lock(&vcpu->kvm->arch.config_lock); + ret = set_id_reg(vcpu, rd, val); + if (ret) { mutex_unlock(&vcpu->kvm->arch.config_lock); - } else { - /* We can only differ with PMUver, and anything else is an error */ - val ^= read_id_reg(vcpu, rd); - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); - if (val) - return -EINVAL; + return ret; + } + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |= + FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), pmuver_to_perfmon(pmuver)); + + if (!valid_pmu) assign_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags, pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF); - } + mutex_unlock(&vcpu->kvm->arch.config_lock); return 0; } @@ -610,7 +615,7 @@ static struct id_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = { .get_user = get_id_reg, .set_user = set_id_aa64dfr0_el1, }, .ftr_bits = ftr_id_aa64dfr0, - .writable_mask = ID_AA64DFR0_EL1_PMUVer_MASK, + .writable_mask = GENMASK(63, 0), .read_kvm_sanitised_reg = read_sanitised_id_aa64dfr0_el1, }, ID_SANITISED(ID_AA64DFR1_EL1),