| Message ID | 20230406061314.10916-5-quic_devipriy@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add APSS clock controller support for IPQ9574 | expand |
On 6.04.2023 08:13, Devi Priya wrote: > Add the APCS & A73 PLL nodes to support CPU frequency scaling. > > Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > Changes in V3: > - No change > > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > index 068c3950dcec..7c820463a79d 100644 > --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > @@ -525,6 +525,24 @@ > timeout-sec = <30>; > }; > > + apcs_glb: mailbox@b111000 { > + compatible = "qcom,ipq9574-apcs-apps-global", > + "qcom,ipq6018-apcs-apps-global"; > + reg = <0x0b111000 0x1000>; > + #clock-cells = <1>; > + clocks = <&a73pll>, <&xo_board_clk>; > + clock-names = "pll", "xo"; > + #mbox-cells = <1>; > + }; > + > + a73pll: clock@b116000 { > + compatible = "qcom,ipq9574-a73pll"; > + reg = <0x0b116000 0x40>; > + #clock-cells = <0>; > + clocks = <&xo_board_clk>; > + clock-names = "xo"; > + }; > + > timer@b120000 { > compatible = "arm,armv7-timer-mem"; > reg = <0x0b120000 0x1000>;
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 068c3950dcec..7c820463a79d 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -525,6 +525,24 @@ timeout-sec = <30>; }; + apcs_glb: mailbox@b111000 { + compatible = "qcom,ipq9574-apcs-apps-global", + "qcom,ipq6018-apcs-apps-global"; + reg = <0x0b111000 0x1000>; + #clock-cells = <1>; + clocks = <&a73pll>, <&xo_board_clk>; + clock-names = "pll", "xo"; + #mbox-cells = <1>; + }; + + a73pll: clock@b116000 { + compatible = "qcom,ipq9574-a73pll"; + reg = <0x0b116000 0x40>; + #clock-cells = <0>; + clocks = <&xo_board_clk>; + clock-names = "xo"; + }; + timer@b120000 { compatible = "arm,armv7-timer-mem"; reg = <0x0b120000 0x1000>;
Add the APCS & A73 PLL nodes to support CPU frequency scaling. Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> --- Changes in V3: - No change arch/arm64/boot/dts/qcom/ipq9574.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)