| Message ID | 20230425131607.290707-2-j-choudhary@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add peripherals for J784S4 | expand |
On 5/15/2023 1:06 PM, Siddharth Vadapalli wrote: > Achal, > > On 15/05/23 11:25, Verma, Achal wrote: >> Hi, >> >> On 4/25/2023 6:46 PM, Jayesh Choudhary wrote: >>> From: Siddharth Vadapalli <s-vadapalli@ti.com> >>> >>> The system controller node manages the CTRL_MMR0 region. >>> Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux. >>> >>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> >>> [j-choudhary@ti.com: Add reg property to fix dtc warning] >>> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> >>> --- >>> arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 23 ++++++++++++++++++++++ >>> 1 file changed, 23 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi >>> b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi >>> index e9169eb358c1..29be6d28ee31 100644 >>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi >>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi >>> @@ -5,6 +5,9 @@ >>> * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ >>> */ >>> +#include <dt-bindings/mux/mux.h> >>> +#include <dt-bindings/mux/ti-serdes.h> >>> + >>> &cbass_main { >>> msmc_ram: sram@70000000 { >>> compatible = "mmio-sram"; >>> @@ -26,6 +29,26 @@ l3cache-sram@200000 { >>> }; >>> }; >>> + scm_conf: syscon@100000 { >> Please check syscon address. > > 0x100000 is the base address of the CTRL_MMR module. Could you please clarify > why the address is incorrect? The registers for J784S4 SoC can be viewed at: > https://www.ti.com/lit/zip/spruj52 I got the doubt because of the address used in this [1] series was different. Now I realized that it was wrong and it got corrected in this patch. So yeah its clear now, 0x100000 is indeed the correct base address. [1] https://serenity.dal.design.ti.com/patchwork/project/linux-patch-review/patch/20220927202534.17148-3-mranostay@ti.com/ > >> >> Thanks, >> Achal Verma >>> + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; >>> + reg = <0x00 0x00100000 0x00 0x1c000>; >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + ranges = <0x00 0x00 0x00100000 0x1c000>; >>> + >>> + serdes_ln_ctrl: mux-controller@4080 { >>> + compatible = "mmio-mux"; >>> + reg = <0x00004080 0x30>; >>> + #mux-control-cells = <1>; >>> + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 >>> select */ >>> + <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */ >>> + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ >>> + <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */ >>> + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ >>> + <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */ >>> + }; >>> + }; >>> + >>> gic500: interrupt-controller@1800000 { >>> compatible = "arm,gic-v3"; >>> #address-cells = <2>; >
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index e9169eb358c1..29be6d28ee31 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -5,6 +5,9 @@ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ */ +#include <dt-bindings/mux/mux.h> +#include <dt-bindings/mux/ti-serdes.h> + &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; @@ -26,6 +29,26 @@ l3cache-sram@200000 { }; }; + scm_conf: syscon@100000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00 0x00100000 0x00 0x1c000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x00100000 0x1c000>; + + serdes_ln_ctrl: mux-controller@4080 { + compatible = "mmio-mux"; + reg = <0x00004080 0x30>; + #mux-control-cells = <1>; + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ + <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */ + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ + <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */ + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ + <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */ + }; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>;