From patchwork Thu May 4 06:07:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13230794 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72224C7EE21 for ; Thu, 4 May 2023 06:08:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=aF6rDCPzQ3fnRfF0KXdfdgQeK9sb7g7/54ZiHINFxPQ=; b=WbwdutrixdnTbZ S4wyrcZnYJigScNn3xywNHBRiz6EvxUFkiUvSib/lMj35uQ4jCotZmqu6f5PurCZqJ4Ayzzt6e9n7 fX9XS4+4NVQBNgfe8w7zt92uMB4gm/mKLI9n5HZpzi/BSVyauFPbuUNj8Ad56YyMVj61DS9JL9ZUT axIRwkaq/2yZncyyrZnc+GL1gX85VSFauE9liCvLFhTwDzEmLV4hb1UGYFGmvz6ktWYa1i2qt6Vwd H5qF2g3qNFmmtySWxRdpV5SQNT9kmpaXPc1YlZ8UM3CYebYcl2tDM/uKlE22wKZVRujI0yH4DlDMY cNwlptiKe7uRdMMas4pQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1puS8L-006hp2-1C; Thu, 04 May 2023 06:08:05 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1puS8H-006hmc-1k for linux-arm-kernel@lists.infradead.org; Thu, 04 May 2023 06:08:03 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1683180481; x=1714716481; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=d8Bl763E9orTffjYX7EPkLY1I0eeSGGed0NMzTMcGWI=; b=KvpEi3fjgfOboq+9XookSTywI4tLyE1COtkZhKc7wOaLsJT4qphH1iDk /BA9kN5hVohuRAH4jGZNiLGd0seSWPs8hCwZ7na9aqQpANp5lFN0p8T2C Y4DxyKwyrmY875KhCHxN6fjLVHipkohun88N6b0wJSuRy22Hb3eDOWKFa lLwL475o64/PX0JsNkoa+KPcmxsaWOYJTOHrkTU5CHFegkhBn274dOaiS 3Hzy+1oevveLVuuhKjpgDsrSx9tevTUJQDyraeD+IJ7PIW3qE2ZpQffW8 odNOFRQisDAiyFi9MrGzVKYqW61IMVis0lVMOIdM0D/mKsHYcLwBQ4+FF g==; X-IronPort-AV: E=Sophos;i="5.99,249,1677567600"; d="scan'208";a="150277158" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 May 2023 23:08:00 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Wed, 3 May 2023 23:07:59 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Wed, 3 May 2023 23:07:55 -0700 From: Claudiu Beznea To: , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH 5/5] dt-bindings: clocks: at91sam9x5-sckc: convert to yaml Date: Thu, 4 May 2023 09:07:29 +0300 Message-ID: <20230504060729.689579-6-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230504060729.689579-1-claudiu.beznea@microchip.com> References: <20230504060729.689579-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230503_230801_639915_764E85AD X-CRM114-Status: GOOD ( 14.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert Atmel slow clock controller documentation to yaml. Signed-off-by: Claudiu Beznea --- .../devicetree/bindings/clock/at91-clock.txt | 30 ------- .../bindings/clock/atmel,at91sam9x5-sckc.yaml | 84 +++++++++++++++++++ 2 files changed, 84 insertions(+), 30 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/at91-clock.txt create mode 100644 Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt deleted file mode 100644 index 57394785d3b0..000000000000 --- a/Documentation/devicetree/bindings/clock/at91-clock.txt +++ /dev/null @@ -1,30 +0,0 @@ -Device Tree Clock bindings for arch-at91 - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Slow Clock controller: - -Required properties: -- compatible : shall be one of the following: - "atmel,at91sam9x5-sckc", - "atmel,sama5d3-sckc", - "atmel,sama5d4-sckc" or - "microchip,sam9x60-sckc": - at91 SCKC (Slow Clock Controller) -- #clock-cells : shall be 1 for "microchip,sam9x60-sckc" otherwise shall be 0. -- clocks : shall be the input parent clock phandle for the clock. - -Optional properties: -- atmel,osc-bypass : boolean property. Set this when a clock signal is directly - provided on XIN. - -For example: - sckc@fffffe50 { - compatible = "atmel,at91sam9x5-sckc"; - reg = <0xfffffe50 0x4>; - clocks = <&slow_xtal>; - #clock-cells = <0>; - }; - diff --git a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml new file mode 100644 index 000000000000..62660c823ea1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/clock/atmel,at91sam9x5-sckc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Atmel Slow Clock Controller (SCKC) + +maintainers: + - Claudiu Beznea + +properties: + compatible: + oneOf: + - items: + - enum: + - atmel,at91sam9x5-sckc + - atmel,sama5d4-sckc + - atmel,sama5d3-sckc + - microchip,sam9x60-sckc + - items: + - const: microchip,sama7g5-sckc + - const: microchip,sam9x60-sckc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#clock-cells": + enum: [0, 1] + + atmel,osc-bypass: + type: boolean + description: set when a clock signal is directly provided on XIN + +required: + - compatible + - reg + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - microchip,sam9x60-sckc + - microchip,sama7g5-sckc + then: + properties: + "#clock-cells": + const: 1 + required: + - "#clock-cells" + - clocks + else: + properties: + "#clock-cells": + const: 0 + if: + properties: + compatible: + contains: + enum: + - atmel,sama5d4-sckc + - atmel,sama5d3-sckc + then: + required: + - "#clock-cells" + - clocks + +examples: + - | + clk32k: clock-controller@fffffe50 { + compatible = "microchip,sam9x60-sckc"; + reg = <0xfffffe50 0x4>; + clocks = <&slow_xtal>; + #clock-cells = <1>; + }; + +...